Vertical transistor having uniform bottom spacers

• US 9,627,511 B1
• Filed: 06/21/2016
• Issued: 04/18/2017
• Est. Priority Date: 06/21/2016
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Zhang, Qintao, Cheng, Kangguo, Li, Juntao, Wang, Geng
• Primary Examiner(s): Harrison, Monica D
• Application Number:
  US15/188,476
• Time in Patent Office: 301 Days
• Field of Search: 257329
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1037 and non-planar channel resulting from the gate electrode disposition, e.g. within a trench, H01L29/42356
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66553 using inside spacers, permanent or not
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A method of forming a spacer for a vertical transistor is provided. The method includes forming a fin structure that includes a fin on a semiconductor substrate, forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin and epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

Claims

1. A method of forming a spacer for a vertical transistor, the method comprising:

forming a fin structure comprising a fin on a semiconductor substrate;

forming a source junction or a drain junction at an upper surface of the semiconductor substrate and at a base of the fin; and

epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the source or drain junction and on opposite sides of the fin structure.

2. The method according to claim 1, further comprising forming a sacrificial spacer on a sidewall of the fin by deposition and reactive ion etch (REI) processing.

3. The method according to claim 2, further comprising replacing at least a portion of the sacrificial spacer by removing an upper portion of the sacrificial spacer remote from the respective upper surfaces of the source or drain junction while maintaining a lower portion of the sacrificial spacer proximate to the respective upper surfaces of the source or drain junction.

4. The method according to claim 2, further comprising replacing the sacrificial spacer by removing an entirety of the sacrificial spacer.

5. The method according to claim 1, wherein the forming of the source or drain junction comprises at least one or more of plasma doping followed by annealing processing and ion implantation processing.

6. The method according to claim 1, wherein the epitaxial growing of the REO spacer comprises at least one of atomic laser deposition (ALD) processing and pulsed laser deposition (PLD) processing.

7. The method according to claim 1, wherein the REO spacer comprises at least one of a single crystallized rare earth metal and a combination of crystallized rare earth metals.

8. The method according to claim 1, wherein the REO spacer has a thickness of about 1-10 nm.

9. The method according to claim 1, wherein the REO spacer has a thickness of about 3-5 nm.

10. A method of forming a uniform spacer for vertical transistors, the method comprising:

forming first and second fin structures on a semiconductor substrate, the first and second fin structures each comprising a fin and sacrificial spacers on respective sidewalls of the fin;

forming source/drain (S/D) junctions at an upper surface of the semiconductor substrate and at respective bases of the fins of each of the first and second fin structures;

epitaxially growing a rare earth oxide (REO) spacer to have a substantially uniform thickness along respective upper surfaces of the S/D junctions between and at opposite sides of each of the first and second fin structures; and

replacing at least respective portions of the sacrificial spacer of each of the first and second fin structures with components of the vertical transistors.

11. The method according to claim 10, wherein the forming of the sacrificial spacer of each of the first and second fin structures comprises deposition and reactive ion etch (RIE) processing.

12. The method according to claim 10, wherein the forming of the S/D junctions comprises at least one or more of plasma doping followed by annealing processing and ion implantation processing.

13. The method according to claim 10, wherein the epitaxial growing of the REO spacer comprises at least one of atomic laser deposition (ALD) processing and pulsed laser deposition (PLD) processing.

14. The method according to claim 10, wherein the REO spacer comprises at least one of a single crystallized rare earth metal and a combination of crystallized rare earth metals.

15. The method according to claim 10, wherein the REO spacer has a thickness of about 1-10 nm.

16. The method according to claim 10 wherein the REO spacer has a thickness of about 3-5 nm.

17. The method according to claim 10, wherein the replacing of at least the respective portions of the sacrificial spacer of each of the first and second fin structures comprises:

removing respective upper sacrificial spacer portions remote from the upper surfaces of the S/D junctions; and

maintaining respective lower sacrificial spacer portions proximate to the upper surfaces of the S/D junctions.

18. The method according to claim 10, wherein the replacing of at least the respective portions of the sacrificial spacer of each of the first and second fin structures comprises removing entireties of the sacrificial spacers.

19. A vertical transistor structure, comprising:

a semiconductor substrate;

first and second fins extending upwardly from first and second doped regions of the semiconductor substrate, respectively;

first and second vertical transistor structures disposed on the first and second fins, respectively; and

an epitaxially grown rare earth oxide (REO) spacer with a substantially uniform thickness which is disposed between respective upper surfaces of the first and second doped regions of the semiconductor substrate and respective lower surfaces of the first and second vertical transistor structures and between and at opposite sides of the first and second fins.

20. The vertical transistor structure according to claim 19, further comprising divot portions formed from sacrificial spacers disposed between the REO spacer and the opposite sides of the first and second fins.