Method of manufacturing thin-film transistor substrate

• US 9,627,515 B2
• Filed: 07/01/2014
• Issued: 04/18/2017
• Est. Priority Date: 10/03/2013
• Status: Active Grant

• Current Assignee: JDI Design and Development GK
• Original Assignee: JOLED Inc.
• Inventors: Satoh, Eiichi
• Primary Examiner(s): Oh, Jaehwan
• Application Number:
  US15/025,389
• Publication Number:
  US 20160240632A1
• Time in Patent Office: 1,022 Days
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/02592 amorphous
• CPC Class Codes: H01L 21/465 Chemical or electrical treatment, e.g. electrolytic etching to form insulating layers H01L21/469
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/76804 by forming tapered via holes
• CPC Class Codes: H01L 23/53233 Copper alloys
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 29/41 characterised by their shape, relative sizes or dispositions
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method of manufacturing a thin-film transistor substrate that includes a thin-film transistor having a semiconductor layer, includes: forming a CuMn alloy film (third conductive film) above a substrate; forming a first silicon oxide film (first insulation film) on the CuMn alloy film at a first temperature; forming an aluminum oxide film (second insulation film) on the first silicon oxide film; and forming a second silicon oxide film (third insulation film) on the aluminum oxide film at a second temperature higher than the first temperature.

Claims

1. A method of manufacturing a thin-film transistor substrate that includes a thin-film transistor having a semiconductor layer, the method of manufacturing the thin-film transistor substrate comprising:

forming a CuMn alloy film above a substrate;

forming a first silicon oxide film on the CuMn alloy film at a first temperature;

forming an aluminum oxide film on the first silicon oxide film; and

forming a second silicon oxide film on the aluminum oxide film at a second temperature higher than the first temperature.

2. The method of manufacturing the thin-film transistor substrate according to claim 1,

wherein the first temperature is 230°

C. or lower.

3. The method of manufacturing the thin-film transistor substrate according to claim 2,

wherein the second temperature is 290°

C. or higher.

4. The method of manufacturing the thin-film transistor substrate according to claim 1, further comprising

forming an opening through a stacked film composed of the first silicon oxide film, the aluminum oxide film, and the second silicon oxide film,

wherein the forming of the opening includes processing the aluminum oxide film by wet etching.

5. The method of manufacturing the thin-film transistor substrate according to claim 4,

wherein the forming of the opening further includes:

processing the second silicon oxide film by dry etching, before the processing of the aluminum oxide film; and

processing the first silicon oxide film by dry etching, after the processing of the aluminum oxide film.

6. The method of manufacturing the thin-film transistor substrate according to claim 1, further comprising:

forming a gate electrode above the substrate;

forming a gate insulation film on the gate electrode;

forming the semiconductor layer on the gate insulation film; and

forming a source electrode and a drain electrode to connect to the semiconductor layer,

wherein the forming of the source electrode and the drain electrode includes the forming of the CuMn alloy film.

7. The method of manufacturing the thin-film transistor substrate according to claim 6,

wherein the forming of the source electrode and the drain electrode further includes:

forming a Mo film;

forming a Cu film on the Mo film; and

the forming of the CuMn alloy film on the Cu film.

8. The method of manufacturing the thin-film transistor substrate according to claim 6,

wherein the forming of the source electrode and the drain electrode further includes:

forming a first CuMn alloy film;

forming a Cu film on the first CuMn alloy film; and

the forming of the CuMn alloy film on the Cu film as a second CuMn alloy film.

9. The method of manufacturing the thin-film transistor substrate according to claim 1,

wherein the first silicon oxide film and the second silicon oxide film are deposited by plasma CVD.

10. The method of manufacturing the thin-film transistor substrate according to claim 1,

wherein the semiconductor layer is an oxide semiconductor layer.

11. The method of manufacturing the thin-film transistor substrate according to claim 10,

wherein the oxide semiconductor layer is a transparent amorphous oxide semiconductor.

12. The method of manufacturing the thin-film transistor substrate according to claim 1,

wherein the CuMn alloy film is a part of wiring.