MOS transistor having a cell array edge zone arranged partially below and having an interface with a trench in an edge region of the cell array

• US 9,627,520 B2
• Filed: 01/28/2016
• Issued: 04/18/2017
• Est. Priority Date: 08/03/2006
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Hirler, Franz, Siemieniec, Ralf, Geissler, Christian, Blank, Oliver, Roesch, Maximilian
• Primary Examiner(s): Jung, Michael
• Application Number:
  US15/009,096
• Publication Number:
  US 20160225884A1
• Time in Patent Office: 446 Days
• Field of Search: None
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0623 Buried supplementary region, e.g. buried guard ring multi-RESURF H01L29/0634
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0661 specially adapted for altering the breakdown voltage by removing semiconductor material at, or in the neighbourhood of, a reverse biased junction, e.g. by bevelling, moat etching, depletion etching
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/1045 the doping structure being parallel to the channel length, e.g. DMOS like
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66674 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region making lateral high-voltage MISFETs with channel well and drain offset region H01L29/66659
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/872 : Schottky diodes

Abstract

A semiconductor component is disclosed. One embodiment includes a semiconductor body including a first semiconductor layer having at least one active component zone, a cell array with a plurality of trenches, and at least one cell array edge zone. The cell array edge zone is only arranged in an edge region of the cell array, adjoining at least one trench of the cell array, and being at least partially arranged below the at least one trench in the cell array.

Claims

1. An MOS transistor, comprising:

a cell array with a plurality of trenches in a semiconductor body, each trench including a field electrode and a field electrode dielectric, the cell array including an edge region, wherein the edge region of the cell array includes both at least an outermost trench of the cell array and a trench of the cell array adjacent to the outermost trench;

at least one cell array edge zone, the at least one cell array edge zone arranged only in the edge region of the cell array at least partially below and having an interface with at least one trench in the edge region of the cell array, wherein the cell array edge zone is spaced apart from a first side of the semiconductor body; and

a plurality of transistor cells in the cell array, each transistor cell comprising a source zone, a drift zone, a body zone arranged between the source zone and the drift zone and adjoining the drift zone, a drain zone spaced apart from the body zone in a direction of a second side opposite the first side of the semiconductor body, and a gate electrode insulated from the body zone by a gate dielectric,

wherein the drift zone has a first conductivity type, and the body zone and the cell array edge zone have a second conductivity type complementary to the first conductivity type,

wherein the body zone is electrically connected to a source electrode, and

wherein the drain zone is spaced apart from the plurality of trenches of the cell array in the direction of the second side.

2. The MOS transistor of claim 1, wherein the gate electrode of each transistor cell of the plurality of transistor cells is arranged in a respective one of the plurality of trenches.

3. The MOS transistor of claim 1,

wherein the semiconductor body comprises a semiconductor body inner region and a semiconductor body edge region,

wherein the drift region of each transistor cell of the plurality of transistor cells is formed by a semiconductor layer of the first conductivity type,

wherein the first semiconductor layer extends across the semiconductor body inner region and the semiconductor body edge region,

and wherein the plurality of transistor cells are only in the semiconductor body inner region.

4. The MOS transistor of claim 3, further comprising:

an edge structure in the semiconductor body edge region.

5. The MOS transistor of claim 4, wherein the edge structure comprises:

at least one edge trench extending from the first side into the semiconductor body;

a dielectric layer in the semiconductor body edge region; and

a first edge zone of the second conductivity type adjoining the at least one edge trench and being at least partially disposed below the at least one edge trench.

6. The MOS transistor of claim 5, wherein the cell array edge zone adjoins the first edge zone in the lateral direction of the semiconductor body.

7. The MOS transistor of claim 6, wherein the outermost trench of the cell array is adjacent to the at least one edge trench, and wherein the cell array edge zone adjoins the outermost trench of the cell array.

8. The MOS transistor of claim 7, wherein the outermost trench is ring-shaped and terminates the cell array in a lateral direction of the semiconductor body.

9. The MOS transistor of claim 5, wherein the cell array edge zone is distant to the first edge zone.

10. The MOS transistor of claim 5, further comprising:

an edge electrode in at least one edge trench, the edge electrode separated from the semiconductor body by the dielectric layer.

11. The MOS transistor of claim 10, wherein the at least one edge trench is completely filled with the edge dielectric.

12. The MOS transistor of claim 10, wherein the edge electrode is electrically coupled to a semiconductor zone doped complementary to a basic doping of the semiconductor layer and arranged between the at least one edge trench and the inner region.

13. The MOS transistor of claim 12, wherein the semiconductor zone adjoins the at least one edge trench.

14. The MOS transistor of claim 5, further comprising:

a second edge zone of the second conductivity type separated from the first edge zone, laterally adjoining the at least one edge trench and adjoining the first side.

15. The MOS transistor of claim 5, wherein the first edge zone has a doping concentration such that the first edge zone can be completely depleted or can be depleted except for an area having dimensions smaller than a lateral width of the edge trench when a transistor of which the at least one trench of the cell array is a part is in an off-state.

16. The MOS transistor of claim 3, wherein the semiconductor layer comprises a first partial layer and a second partial layer, wherein the second partial layer is below the first partial layer as seen from the first side and has a lower doping concentration than the first partial layer.

17. The MOS transistor of claim 1, wherein the edge region of the cell array extends along an edge of the cell array and has a size of between 0.1% and 2% of a size of the cell array in a horizontal plane of the semiconductor body.

18. The MOS transistor of claim 1, wherein the cell array edge zone of the cell array is ring-shaped in a horizontal plane of the semiconductor body.

19. The MOS transistor of claim 1, wherein the at least one cell array edge zone has a doping concentration such that the cell array edge zone can be completely depleted or can be depleted except for an area having dimensions smaller than a lateral width of the edge trench when a transistor of which the at least one trench of the cell array is a part is in an off-tate.

20. The MOS transistor of claim 1, further comprising:

at least two edge trenches, the at least two edge trenches being disposed distant to each other in a lateral direction of the semiconductor body; and

a number of first edge zones corresponding to the number of trenches.

21. The MOS transistor of claim 20, comprising a number of second edge zones corresponding to the number of trenches, with each of the second edge zones adjoining one edge trench in a direction opposite to the direction of the inner region.

22. The MOS transistor of claim 21, wherein each of the second edge zones is disposed between two edge trenches and extend in a lateral direction from trench to trench.

23. The semiconductor component of claim 1, wherein the edge region of the cell array includes fewer than all trenches of the cell array.

24. The MOS transistor of claim 23, wherein the plurality of trenches of the cell array extend into the second partial layer.

25. The MOS transistor of claim 1, wherein the cell array edge zone is spaced apart from the drain zone and separated from the drain zone by a second of the drift zone.

26. The MOS transistor of claim 1, wherein the plurality of trenches of the cell array, in the direction of the second side, end in the drift region.

27. The MOS transistor of claim 1, wherein the drain zone adjoins the drift zone.

28. The MOS transistor of claim 1, wherein the drain zone is spaced apart from the cell array edge zone in the direction of the second side of the semiconductor body.

29. The MOS transistor of claim 1, wherein a second of the drift zone is arranged between the cell array edge zone and the drain zone.