LEDs with efficient electrode structures

• US 9,627,589 B2
• Filed: 04/29/2016
• Issued: 04/18/2017
• Est. Priority Date: 05/19/2006
• Status: Active Grant

• Current Assignee: Bridgelux Incorporated
• Original Assignee: Bridgelux Incorporated
• Inventors: Shum, Frank T., So, William W., Lester, Steven D.
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US15/143,423
• Publication Number:
  US 20160247975A1
• Time in Patent Office: 354 Days
• Field of Search: 257 76, 257 79, 257 80, 257 96, 257 98, 257 99, 257E33005, 257E33061, 257E33067, 257E33068, 257E27121, 257E21002, 372 3809, 372 4301, 372 50124, 438 29, 438 31, 438 32
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/20 with a particular shape, e.g. curved or truncated substrate
• CPC Class Codes: H01L 33/24 of the light emitting region, e.g. non-planar junction
• CPC Class Codes: H01L 33/32 containing nitrogen
• CPC Class Codes: H01L 33/38 with a particular shape
• CPC Class Codes: H01L 33/382 the electrode extending partially in or entirely through the semiconductor body
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/387 with a plurality of electrode regions in direct contact with the semiconductor body and being electrically interconnected by another electrode layer
• CPC Class Codes: H01L 33/405 Reflective materials
• CPC Class Codes: H01L 33/42 Transparent materials
• CPC Class Codes: H01L 33/44 characterised by the coatings, e.g. passivation layer or anti-reflective coating
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

Aspects include Light Emitting Diodes that have a GaN-based light emitting region and a metallic electrode. The metallic electrode can be physically separated from the GaN-based light emitted region by a layer of porous dielectric, which provides a reflecting region between at least a portion of the metallic electrode and the GaN-based light emitting region.

Claims

1. A semiconductor structure, comprising:

a first doped region disposed on a second doped region to form an active region therebetween for generating light;

a cutout defined by a partial removal of material from the first doped region to expose a surface of the second doped region;

a dielectric disposed only on the surface in a first region of the cutout; and

an electrode comprising a first portion disposed on the dielectric and a second portion disposed on the surface in a second region of the cutout.

2. The semiconductor structure of claim 1, wherein the cutout comprises at least one parameter predetermined to increase an amount of light emitted from a surface of the first doped region.

3. The semiconductor structure of claim 2, wherein the at least one parameter comprises an area of the cutout.

4. The semiconductor structure of claim 1, wherein the cutout comprises at least one parameter selected based on a desired bonding area for the electrode.

5. The semiconductor structure of claim 1, further comprising:

a second dielectric disposed on a surface of the first doped region; and

a second electrode comprising a first portion disposed on the second dielectric and a second portion disposed on the surface of the first doped region.

6. The semiconductor structure of claim 1, wherein the surface of the second doped region is substantially parallel with a surface of the first doped region.

7. The semiconductor structure of claim 1, wherein the dielectric comprises a reflective dielectric.

8. The semiconductor structure of claim 1, further comprising an ohmic layer disposed between the surface of the second doped region on one hand, and the dielectric and the electrode on the other hand.

9. An electrode structure for a light-emitting diode (LED), comprising:

a semiconductor comprising a first doped region disposed on a second doped region;

a cutout exposing a surface of the second doped region;

a dielectric formed only on the surface in a first region of the cutout; and

an electrode formed partially on the dielectric and partially on the surface in a second region of the cutout.

10. The electrode structure of claim 9, wherein the cutout comprises at least one parameter predetermined to increase an amount of light emitted from a surface of the first doped region.

11. The electrode structure of claim 10, wherein the at least one parameter comprises an area of the cutout.

12. The electrode structure of claim 9, wherein the cutout comprises at least one parameter selected based on a desired bonding area for the electrode.

13. The electrode structure of claim 9, further comprising:

a second dielectric disposed on a surface of the first doped region; and

a second electrode comprising a first portion disposed on the second dielectric and a second portion disposed on the surface of the first doped region.

14. The electrode structure of claim 9, wherein the surface of the second doped region is substantially parallel with a surface of the first doped region.

15. The electrode structure of claim 9, wherein the dielectric comprises a reflective dielectric.

16. The electrode structure of claim 9, further comprising an ohmic layer disposed between the surface of the second doped region on one hand, and the dielectric and the electrode on the other hand.

17. A semiconductor structure, comprising:

a first doped region disposed on and electrically coupled to a second doped region via an active region formed therebetween, the active region configured to generate light for emission through a surface of the first doped region;

a bonding area defined by a removal of a portion of the first doped region to expose a surface of the second doped region;

a dielectric disposed only over a first portion of the exposed surface; and

a metal bond pad formed partially on the dielectric and partially on a second portion of the exposed surface.

18. The semiconductor structure of claim 17, wherein a size of the bonding area is predetermined based on one or more electrical characteristics.

19. The semiconductor structure of claim 18, wherein the one or more electrical characteristics comprise an amount of current carried through the metal bond pad.

20. The semiconductor structure of claim 18, wherein the one or more electrical characteristics comprise an amount of light emitted from the surface of the first doped region.