High speed grounded communication jack

• US 9,627,816 B2
• Filed: 05/04/2016
• Issued: 04/18/2017
• Est. Priority Date: 02/13/2012
• Status: Active Grant

• Current Assignee: Sentinel Connector Systems, Inc.
• Original Assignee: Sentinel Connector Systems, Inc.
• Inventors: Robinson, Brett D., Wagner, Justin
• Primary Examiner(s): GUSHI, ROSS N
• Application Number:
  US15/146,019
• Publication Number:
  US 20160248205A1
• Time in Patent Office: 349 Days
• CPC Class Codes: H01R 13/6474 by variation of conductive properties, e.g. by dimension variations
• CPC Class Codes: H01R 13/6581 Shield structure
• CPC Class Codes: H01R 13/6658 on printed circuit board H01R13/6666 - H01R13/6691 take precedence
• CPC Class Codes: H01R 2107/00 Four or more poles
• CPC Class Codes: H01R 24/64 for high frequency, e.g. RJ 45
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of manufacturing a high speed jack, the method including the steps of forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug, forming a shielding case surrounding the housing, forming a top layer of a substrate, a first shielding layer on a first side of the top layer in the substrate, a second shielding layer adjacent the first shielding layer in the substrate, and forming a bottom layer adjacent to the second shielding layer, forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing, forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing.

Claims

1. A high speed communication jack including:

a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;

a shielding case surrounding the housing;

a circuit board in the housing having

a substrate,

a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing,

a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing,

a first set of traces on a top layer of the substrate that connects at least one first via with at least one corresponding second via;

a first shielding layer on a first side of the top layer in the substrate;

a second shielding layer adjacent the first shielding layer in the substrate; and

a second set of traces on a side of the substrate opposite the top layer that connects at least one first via with at least one second via.

2. The jack of claim 1 wherein the second set of traces connect different vias that the vias connected on the top surface.

3. The jack of claim 1 including a first isolation region on the top surface between the first set of traces.

4. The jack of claim 1 including a second isolation region on the top surface between a second set of traces.

5. The jack of claim 1 wherein the first shielding layer is covered in a conductive material.

6. The jack of claim 5 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

7. The jack of claim 5 wherein the conductive material is comprised of copper and finished silver.

8. The jack of claim 1 wherein the second shielding layer is covered in a conductive material.

9. The jack of claim 8 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

10. The jack of claim 8 wherein the conductive material is comprised of copper and finished silver.

11. A method of manufacturing a high speed jack, the method including the steps of

forming a housing including a port for accepting a plug, the port including a plurality of pins each connected to a corresponding signal line in the plug;

forming a shielding case surrounding the housing;

forming a top layer of a substrate,

a first shielding layer on a first side of the top layer in the substrate;

a second shielding layer adjacent the first shielding layer in the substrate; and

forming a bottom layer adjacent to the second shielding layer,

forming a plurality of first vias extending through the substrate with each first via being configured to accommodate a pin on the housing,

forming a plurality of second vias extending through the substrate with each second via being configured to accommodate a pin on the housing,

forming a first set of traces on a top layer of the substrate that connects at least one first via with at least one corresponding second via;

forming a second set of traces on a side of the substrate opposite the top layer that connects at least one first via with at least one second via.

12. The method of claim 11, wherein the second set of traces connect different vias that the vias connected on the top surface.

13. The method of claim 11 including the step of forming a first isolation region on the top surface between the first set of traces.

14. The method of claim 11 including the step of forming a second isolation region on the top surface between a second set of traces.

15. The method of claim 11 wherein the first shielding layer is covered in a conductive material.

16. The method of claim 15 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

17. The method of claim 15 wherein the conductive material is comprised of copper and finished silver.

18. The method of claim 11 wherein the second shielding layer is covered in a conductive material.

19. The method of claim 18 wherein the conductive material does not cover an area around the periphery of the first vias and second vias.

20. The method of claim 18 wherein the conductive material is comprised of copper and finished silver.