Voltage generation circuit, flash memory and semiconductor device

• US 9,627,963 B2
• Filed: 02/01/2016
• Issued: 04/18/2017
• Est. Priority Date: 02/04/2015
• Status: Active Grant

• Current Assignee: Winbond Electronics Corporation
• Original Assignee: Winbond Electronics Corporation
• Inventors: Takeshita, Toshiaki
• Primary Examiner(s): Ho, Hoai V
• Assistant Examiner(s): DINH, MINH D
• Application Number:
  US15/012,424
• Publication Number:
  US 20160226377A1
• Time in Patent Office: 442 Days
• Field of Search: 36518518
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A voltage generation circuit is provided to suppress the required layout of the voltage generation circuit and stabilize the output voltage thereof.

[Solution]

A voltage generation circuit 100A according to the present invention includes a charge pump circuit 20, a resistor voltage-division circuit 120, a comparator 34 having a voltage Vm output from the resistor voltage-division circuit 120 and a reference voltage, and a control circuit 36 controlling the operation of the charge pump circuit 20 based on the comparison result of the comparator 34. The resistor voltage-division circuit 120 includes resistors R1˜R4 connected in series between an output node N_OUT and a ground and generates the voltage Vm at a voltage-division node N_R in response to an output voltage V_OUT. The resistor voltage-division circuit 120 further includes a parasitic capacitor Cp to capacitively couple the resistors R1, R2, R3 and R4 to the output node N_OUT.

Claims

1. A voltage generation circuit, comprising:

a conversion circuit converting an input voltage to another voltage level and providing an output voltage after converting, to an output node;

a resistor voltage-division circuit coupled to the output node, generating a voltage corresponding to the output voltage;

a comparison circuit comparing the voltage generated by the resistor voltage-division circuit and a reference voltage; and

a control circuit controlling the conversion circuit based on a comparing result of the comparison circuit,

wherein the resistor voltage-division circuit comprises a capacitor device which is capacitively coupling at least one part of a resistor in the resistor voltage-division circuit to the output node, and

wherein the capacitor device comprises a conductor portion extending from the output node and over the at least one part of a resistor.

2. The voltage generation circuit as claimed in claim 1, wherein the capacitor device comprises a dielectric layer formed between the conductor portion and the resistors.

3. The voltage generation circuit as claimed in claim 2, wherein:

the resistors comprise a first polysilicon layer having conductivity, formed over a substrate;

the conductor portion comprises a second polysilicon layer having conductivity, formed over the first polysilicon layer; and

a dielectric layer is formed between the first and second polysilicon layers.

4. A Flash memory, comprising the voltage generation circuit as claimed in claim 3, wherein:

the first polysilicon layer and a floating gate of a cell of the Flash memory are made of the same material;

the second polysilicon layer and a control gate of the cell are made of the same material; and

the dielectric layer and a dielectric layer formed between the floating gate and the control gate are made of the same material.

5. The voltage generation circuit as claimed in claim 2, wherein:

the resistors comprise a first polysilicon layer having conductivity, formed over a substrate;

the conductor portion is a conductive region in the substrate; and

a dielectric layer is formed between the first polysilicon layer and the conductive region in the substrate.

6. The voltage generation circuit as claimed in claim 2, wherein:

the resistors comprise a first polysilicon layer having conductivity, formed over a substrate;

the conductor portion comprises a second polysilicon layer having conductivity, formed over the first polysilicon layer and a conductive region in the substrate;

a first dielectric layer is formed between the first and second polysilicon layers; and

a second dielectric layer is formed between the first polysilicon layer and the conductive region in the substrate.

7. The voltage generation circuit as claimed in claim 1, wherein the conversion circuit comprises a charge pump circuit.

8. The voltage generation circuit as claimed in claim 7, wherein:

the conversion circuit further comprises a clock circuit which is clock-enabled based on the comparing result of the comparison circuit; and

the charge pump circuit responds to a clock signal from the clock circuit and provides the output voltage to the output node.

9. A semiconductor device, comprising a voltage generation circuit, wherein the voltage generation circuit comprises:

a conversion circuit converting an input voltage to another voltage level and providing an output voltage after converting, to an output node;

a resistor voltage-division circuit coupled to the output node, generating a voltage corresponding to the output voltage;

a comparison circuit comparing the voltage generated by the resistor voltage-division circuit and a reference voltage; and

a control circuit controlling the conversion circuit based on a comparing result of the comparison circuit,

wherein the resistor voltage-division circuit comprises a capacitor device which is capacitively coupling at least one part of a resistor in the resistor voltage-division circuit to the output node, and

wherein the capacitor device comprises a conductor portion extending from the output node and over the at least one part of a resistor.

10. The semiconductor device as claimed in claim 9, wherein the capacitor device comprises a dielectric layer formed between the conductor portion and the resistors.

11. The semiconductor device as claimed in claim 10, wherein:

the resistors comprise a first polysilicon layer having conductivity, formed over a substrate;

the conductor portion comprises a second polysilicon layer having conductivity, formed over the first polysilicon layer; and

a dielectric layer is formed between the first and second polysilicon layers.

12. The semiconductor device as claimed in claim 10, wherein:

the resistors comprise a first polysilicon layer having conductivity, formed over a substrate;

the conductor portion is a conductive region in the substrate; and

a dielectric layer is formed between the first polysilicon layer and the conductive region in the substrate.

13. The semiconductor device as claimed in claim 10, wherein:

the resistors comprise a first polysilicon layer having conductivity, formed over a substrate;

the conductor portion comprises a second polysilicon layer having conductivity, formed over the first polysilicon layer and a conductive region in the substrate;

a first dielectric layer is formed between the first and second polysilicon layers; and

a second dielectric layer is formed between the first polysilicon layer and the conductive region in the substrate.

14. The semiconductor device as claimed in claim 9, wherein the conversion circuit comprises a charge pump circuit.

15. The semiconductor device as claimed in claim 14, wherein:

the conversion circuit further comprises a clock circuit which is clock-enabled based on the comparing result of the comparison circuit; and

the charge pump circuit responds to a clock signal from the clock circuit and provides the output voltage to the output node.