Electronic circuit having dynamic resistance element

• US 9,628,105 B1
• Filed: 10/02/2015
• Issued: 04/18/2017
• Est. Priority Date: 10/02/2015
• Status: Active Grant

• Current Assignee: Senseeker Engineering Inc.
• Original Assignee: Senseeker Engineering Inc.
• Inventors: Veeder, Kenton
• Primary Examiner(s): Sohn, Seung C
• Application Number:
  US14/873,886
• Time in Patent Office: 564 Days
• Field of Search: 2502081
• CPC Class Codes: H03M 3/39 Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators of digital delta-sigma modulators H03M7/3004
• CPC Class Codes: H03M 3/458 Analogue/digital converters using delta-sigma modulation as an intermediate step
• CPC Class Codes: H04N 25/617 for reducing electromagnetic interference, e.g. clocking noise
• CPC Class Codes: H04N 25/75 Circuitry for providing, modifying or processing image signals from the pixel array
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters

Abstract

The present disclosure provides a delta-sigma modulator circuit for use in a pixelated image sensor or a readout integrated circuit. In one aspect, the modulator circuit includes a dynamic resistance element configured to have a variable resistance that changes in accordance with a voltage difference across the dynamic resistance element.

Claims

1. An electronic circuit having a first node, a second node, and a third node, the electronic circuit comprising:

a first capacitor electrically coupled between the first and second nodes;

a second capacitor electrically coupled between the second and third nodes;

a dynamic resistance element electrically coupled between the first and third nodes for receiving a current input signal from the third node, wherein the dynamic resistance element is configured to have a variable resistance that changes in accordance with a voltage difference across the dynamic resistance element;

a charge transfer switch electrically coupled between the first node and the dynamic resistance element to enable charge transfer from the first capacitor to the third node through the dynamic resistance element when the charge transfer switch is closed;

a recharge circuit electrically coupled across the first capacitor to recharge the first capacitor to a common voltage when the charge transfer switch is open; and

a comparator having a first terminal electrically coupled to the third node, a second terminal electrically coupled to a reference voltage, and an output terminal electrically coupled to the charge transfer switch.

2. The electronic circuit of claim 1, wherein the variable resistance, when measured from the first node, changes dynamically as a function of a voltage at the first node and reaches a high resistance state when the voltage at the first node decreases to a predetermined value.

3. The electronic circuit of claim 1, wherein the variable resistance, when measured from the third node, remains at a high resistance state while a voltage at the first node varies.

4. The electronic circuit of claim 1, wherein the dynamic resistance element comprises a gain-boosted transistor element operable at transistor non-linear regions such that, when the charge transfer switch is closed, a source resistance of the gain-boosted transistor element remains at a low value and increases to a high value as a voltage at the first node decreases to a predetermined level such that almost no current is conducted through the gain-boosted transistor element.

5. The electronic circuit of claim 1, wherein the comparator is controlled by a first clock signal, the recharge circuit is controlled by a second clock signal, and the first and second clocks are non-overlapping.

6. The electronic circuit of claim 5, wherein the first clock is ON when the second clock is OFF.

7. The electronic circuit of claim 1, wherein an amount of the charge transferred to the third node corresponds to a conductive range of the dynamic resistance element multiplied by a capacitance value of the first capacitor.

8. The electronic circuit of claim 7, wherein a voltage change in an analog residue at the third node equals a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor, multiplied by the conductive range.

9. The electronic circuit of claim 8, wherein the analog residue is passed to a down stream circuitry for extended counting operation.

10. The electronic circuit of claim 1, wherein the dynamic resistance element comprises:

a first transistor having a first gate electrically coupled to a bias voltage, a first drain, and a first source electrically coupled to a ground;

a second transistor having a second gate electrically coupled to a first terminal of the dynamic resistance element, a second source electrically coupled to a supply voltage, and a second drain electrically coupled to the first drain; and

a third transistor having a third gate electrically coupled to the first drain and the second drain, a third source electrically coupled to the second gate, and a third drain electrically coupled to a second terminal of the dynamic resistance element.

11. The electronic circuit of claim 10, wherein the supply voltage is equal to the common voltage.

12. The electronic circuit of claim 9, wherein the supply voltage is different from the common voltage.

13. A delta-sigma modulator circuit comprising the electronic circuit of claim 1, a digital filter circuit electrically coupled to the output terminal of the comparator, and a decimator circuit electrically coupled to the digital filter circuit for generating a digital output signal.

14. An image sensor comprising an array of photosensitive pixels, each photosensitive pixel comprising a sensing transducer for generating the current input signal, and the delta-sigma modulator circuit of claim 13 electrically coupled to the sensing transducer for processing the current input signal from the sensing transducer.

15. The image sensor of claim 14, wherein the sensing transducer comprise a photon sensitive detector.

16. An electronic circuit having a first node, a second node, and a third node, the electronic circuit comprising:

a first capacitor electrically coupled between the first and second nodes;

a second capacitor electrically coupled between the second and third nodes;

a dynamic resistance element electrically coupled between the first and third nodes, wherein the dynamic resistance element is configured to have a variable resistance that changes in accordance with a voltage difference across the dynamic resistance element;

a charge transfer switch electrically coupled between the first node and the dynamic resistance element to enable charge transfer from the first capacitor to the third node through the dynamic resistance element when the charge transfer switch is closed;

a recharge circuit electrically coupled across the first capacitor to recharge the first capacitor when the charge transfer switch is open, wherein the recharge circuit comprises a reset switch electrically coupled to the first node and a limiter switch electrically coupled to the reset switch; and

a comparator having a first terminal electrically coupled to the third node, a second terminal electrically coupled to a reference voltage, and an output terminal electrically coupled to the charge transfer switch.

17. The electronic circuit of claim 16, wherein the first capacitor is electrically coupled to a first supply voltage from the first node through the reset switch and the limiter switch and electrically coupled to a second supply voltage from the second node.

18. The electronic circuit of claim 17, wherein the first supply voltage is different from the second supply voltage.

19. The electronic circuit of claim 16, wherein the comparator is controlled by a first clock signal, the reset switch is controlled by a second clock signal, and the first clock is ON when the second clock is OFF.

20. The electronic circuit of claim 16, wherein the variable resistance, when measured from the first node, changes dynamically as a function of a voltage at the first node and reaches a high resistance state when the voltage at the first node decreases to a predetermined value.

21. The electronic circuit of claim 16, wherein the variable resistance, when measured from the third node, remains at a high resistance state while a voltage at the first node varies.

22. The electronic circuit of claim 16, wherein the dynamic resistance element comprises a gain-boosted transistor element operable at transistor non-linear regions such that, when the charge transfer switch is closed, a source resistance of the gain-boosted transistor element remains at a low value and increases to a high value as a voltage at the first node decreases to a predetermined level such that almost no current is conducted through the gain-boosted transistor element.

23. The electronic circuit of claim 16, wherein an amount of the charge transferred to the third node corresponds to a conductive range of the dynamic resistance element multiplied by a capacitance value of the first capacitor.

24. The electronic circuit of claim 23, wherein a voltage change in analog residue at the third node equals a ratio of a capacitance value of the first capacitor to a capacitance value of the second capacitor, multiplied by the conductive range.

25. The electronic circuit of claim 24, wherein the analog residue is passed to a down-stream circuitry for extended counting operation.

26. The electronic circuit of claim 16, wherein the dynamic resistance element comprises:

a first transistor having a first gate electrically coupled to a bias voltage, a first drain, and a first source electrically coupled to a ground;

a second transistor having a second gate electrically coupled to a first terminal of the dynamic resistance element, a second source electrically coupled to a supply voltage, and a second drain electrically coupled to the first drain; and

a third transistor having a third gate electrically coupled to the first drain and the second drain, a third source electrically coupled to the second gate, and a third drain electrically coupled to a second terminal of the dynamic resistance element.

27. A delta-sigma modulator circuit comprising the electronic circuit of claim 16, a digital filter circuit electrically coupled to the output terminal of the comparator, and a decimator circuit electrically coupled to the digital filter circuit for generating a digital output signal.

28. An image sensor comprising an array of photosensitive pixels, each photosensitive pixel comprising a sensing transducer for generating the current input signal, and the delta-sigma modulator circuit of claim 27 electrically coupled to the sensing transducer for processing the current input signal from the sensing transducer.

29. The image sensor of claim 28, wherein the sensing transducer comprise a photon sensitive detector.

30. An electronic circuit having a first node, a second node, and a third node, the electronic circuit comprising:

a first capacitor electrically coupled between the first and second nodes;

a second capacitor electrically coupled between the second and third nodes;

a dynamic resistance element electrically coupled between the first and third nodes for receiving a current input signal from the third node, wherein the dynamic resistance element is configured to have a variable resistance that changes in accordance with a voltage difference across the dynamic resistance element;

a charge transfer switch electrically coupled between the first node and the dynamic resistance element to enable charge transfer from the first capacitor to the second capacitor when the charge transfer switch is closed;

a recharge circuit electrically coupled across the first capacitor to recharge the first capacitor to a first supply voltage when the charge transfer switch is open; and

a comparator having a first terminal electrically coupled to the third node, a second terminal electrically coupled to a reference voltage, and an output terminal electrically coupled to the charge transfer switch;

wherein the dynamic resistance element is electrically coupled with a second supply voltage different from the first supply voltage.

31. A readout circuit for processing input signals, the readout circuit comprising:

a first capacitor electrically coupled between a first node and a second node;

a second capacitor electrically coupled between the second node and a third node;

a dynamic resistance element electrically coupled between the first node and the third node, the dynamic resistance element being configured to have a variable resistance that changes in accordance with a voltage value at the first node;

a charge transfer switch electrically coupled between the first node and the dynamic resistance element;

a recharge circuit electrically coupled across the first capacitor; and

a comparator having a first terminal electrically coupled to the third node, a second terminal electrically coupled to a reference voltage, and an output terminal electrically coupled to the charge transfer switch.