Communication channel calibration for drift conditions

• US 9,628,257 B2
• Filed: 11/04/2015
• Issued: 04/18/2017
• Est. Priority Date: 01/28/2004
• Status: Active Grant

• Current Assignee: K.Mizra LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Perego, Richard E., Hampel, Craig E.
• Primary Examiner(s): Tran, Khai
• Application Number:
  US14/932,192
• Publication Number:
  US 20160056948A1
• Time in Patent Office: 531 Days
• Field of Search: 375355, 375219, 375222, 375257, 375295, 370516
• CPC Class Codes: G11C 2207/2254 Calibration
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end
• CPC Class Codes: H04L 25/12 Compensating for variations in line impedance
• CPC Class Codes: H04L 7/0016 correction of synchronization errors
• CPC Class Codes: H04L 7/0087 Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Claims

1. A component, comprising:

a receiver to sample arriving read data, retrieved from addressable memory space of a memory device, the read data arriving at the component via a bidirectional link during a normal mode of operation, the sampling performed according to an operational value of a sampling instant defined relative to a reference clock;

circuitry to suspend the normal mode of operation to update the operational value of the sampling instant in order to account for timing drift, the circuitry to cause the receiver to, in iterations, use at least two other values of the sampling instant to sample values of a predefined data pattern arriving at the component from the memory device via the bidirectional link;

circuitry to, for each value of the at least two other values of the sampling instant, compare the sampled values of the predefined data pattern against expected data, to obtain pass/fail data; and

circuitry to update the operational value of the sampling instant in response to the pass/fail data, to obtain an updated value;

wherein the component is to sample the arriving read data, retrieved from the addressable memory space of the memory device, following resumption of the normal mode of operation according to the updated value.

2. The component of claim 1, wherein:

the component comprises storage to store three different values of the sampling instant, including a first value, a second value, and the operating value;

the circuitry to suspend is to test, when the normal mode is suspended, at least one of the first value or the second value to determine whether the at least one has moved in as a consequence of timing drift, the first value representing one end of a range of sampling instants representing passage of the predefined data pattern relative to the expected data, and the second value representing a second end of the range; and

the circuitry to update is to update the at least one in dependence on the pass/fail data, and is to select the updated value in dependence on the at least one, as updated.

3. The component of claim 2, wherein the circuitry to update is to select the updated value to be the midpoint of the range, as determined from the at least one, as updated.

4. The component of claim 2, wherein the circuitry to update is to select the updated value in dependence on a weighted average of the first value and the second value, as updated.

5. The component of claim 1, wherein the receiver is to sample bits from the link in the normal operating mode at a frequency of not less than 400 megabits per second, and wherein the receiver further comprises a deserializer to deserialize the read data.

6. The component of claim 1, wherein for each of the iterations, the predefined data pattern is to be repeated at least N times for each value of the at least two values of the sampling instant, prior to switching to another value of the sampling instant, wherein N is at least two.

7. The component of claim 1, wherein the predefined data pattern is selected by the component and is written to the memory device prior to being provided from the memory device to the first component in association with the iterations.

8. A component, comprising:

a receiver to sample read data, the read data arriving at the component via a bidirectional link during the normal mode of operation, the sampling performed according to an operational value of a sampling instant defined relative to a reference clock;

circuitry to suspend the normal mode of operation to update the operational value of the sampling instant in order to account for timing drift, and to, in iterations

increment the sampling instant between multiple values of the sampling instant, including at least two values of the sampling instant other than the operational value,

for each one of the multiple values, sample values of a predefined data pattern arriving at the component from the memory device via the bidirectional link, and compare the sampled values of the predefined data pattern against expected data, to obtain pass/fail data corresponding to the one of the multiple values; and

circuitry to update the operational value of the sampling instant in response to the pass/fail data, to obtain an updated value; and

wherein

the circuitry to update the operational value is to select a first value of the sampling instant and a second value of the sampling instant, the first value and the second value representing a range of possible values of the sampling instant for which the pass/fail data represents passage, and is to update the operational value in dependence on the first value and the second value, and

the component is to sample the read data following resumption of the normal mode of operation according to the updated value.

9. The component of claim 8, wherein the circuitry to update is to select the updated value to be the midpoint of the range, as determined from the first value and the second value.

10. The component of claim 8, wherein the circuitry to update is to select the updated value in dependence on a weighted average of the first value and the second value.

11. The component of claim 8, wherein the receiver is to sample bits from the link in the normal operating mode at a frequency of not less than 400 megabits per second, and wherein the receiver further comprises a deserializer to deserialize the read data.

12. The component of claim 8, wherein for each of the iterations, the predefined data pattern is to be repeated at least N times for each value of the at least two values of the sampling instant, prior to switching to another value of the sampling instant, wherein N is at least two.

13. The component of claim 12, wherein the predefined data pattern is selected by the component and is written to the memory device prior to being provided from the memory device to the first component in association with the iterations.

14. A first component to couple electronically to a second component in a memory system, the second component comprising an integrated circuit memory device, the first component to exchange write data and read data with addressable space in the memory device via a bidirectional link during a normal mode of operation, the first component comprising:

a receiver to sample read data from the bidirectional link during the normal mode of operation, according to an operational value of a sampling instant defined relative to a reference clock;

circuitry to suspend the normal mode of operation to update the operational value of the sampling instant in order to account for timing drift, the circuitry to cause the receiver to, in iterations, use at least two other values of the sampling instant to sample values of a predefined data pattern arriving at the component from the memory device via the bidirectional link;

circuitry to, for each value of the at least two other values of the sampling instant, compare the sampled values of the predefined data pattern against expected data, to obtain pass/fail data; and

circuitry to update the operational value of the sampling instant in response to the pass/fail data, to obtain an updated value;

wherein the component is to sample read data from the second component following resumption of the normal mode of operation according to the updated value.

15. The component of claim 14, wherein:

the component comprises storage to store three different values of the sampling instant, including a first value, a second value, and the operating value;

the circuitry to suspend is to test, when the normal mode is suspended, each of the first value and the second value to determine whether the first value or the second value has moved in as a consequence of timing drift, the first value representing one end of a range of sampling instants representing passage of the predefined data pattern relative to the expected data, and the second value representing a second end of the range; and

the circuitry to update is to update the first value and the second value in dependence on the pass/fail data, and is to select the updated value in dependence on the first value and the second value, as updated.

16. The component of claim 15, wherein the circuitry to update is to select the updated value to be the midpoint of the range, as determined from the first value and the second value, as updated.

17. The component of claim 15, wherein the circuitry to update is to select the updated value in dependence on a weighted average of the first value and the second value, as updated.

18. The component of claim 15, wherein the receiver is to sample bits from the link in the normal operating mode at a frequency of not less than 400 megabits per second, and wherein the receiver further comprises a deserializer to deserialize the read data.

19. The component of claim 14, wherein for each of the iterations, the predefined data pattern is to be repeated at least N times for each value of the at least two values of the sampling instant, prior to switching to another value of the sampling instant, wherein N is at least two.

20. The component of claim 14, wherein the predefined data pattern is selected by the component and is written to the memory device prior to being provided from the memory device to the first component in association with the iterations.