Wafer scale monolithic CMOS-integration of free- and non-free-standing Metal- and Metal alloy-based MEMS structures in a sealed cavity

• US 9,630,834 B2
• Filed: 06/16/2014
• Issued: 04/25/2017
• Est. Priority Date: 06/16/2014
• Status: Active Grant

• Current Assignee: Tectus Corporation
• Original Assignee: Insense Inc.
• Inventors: Tayebi, Noureddine, Luo, Hao
• Primary Examiner(s): Manno, Jessica
• Assistant Examiner(s): HAGAN, SEAN P
• Application Number:
  US14/306,139
• Publication Number:
  US 20150360936A1
• Time in Patent Office: 1,044 Days
• CPC Class Codes: B81B 2207/015 the micromechanical device and the control or processing electronics being integrated on the same substrate
• CPC Class Codes: B81B 7/02 containing distinct electrical or optical devices of particular relevance for their function, e.g. microelectro-mechanical systems [MEMS] B81B7/04 takes precedence
• CPC Class Codes: B81C 1/0023 Packaging together an electronic processing unit die and a micromechanical structure die MEMS packages B81B7/0032; MEMS packaging processes B81C1/00261
• CPC Class Codes: B81C 1/00246 Monolithic integration, i.e. micromechanical structure and electronic processing unit are integrated on the same substrate
• CPC Class Codes: B81C 1/00793 Avoid contamination, e.g. absorption of impurities or oxidation
• CPC Class Codes: B81C 2203/0136 Growing or depositing of a covering layer
• CPC Class Codes: B81C 2203/0735 Post-CMOS, i.e. forming the micromechanical structure after the CMOS circuit
• CPC Class Codes: H01L 2224/05014 being square

Abstract

An assembly of metallic MEMS structures directly fabricated on planarized CMOS substrates, containing the application-specific integrated circuit (ASIC), by direct deposition and subsequent microfabrication steps on the ASIC interconnect layers, with integrated capping for packaging, is provided. The MEMS structures comprise at least one MEMS device element, with or without moveable parts anchored on the CMOS ASIC wafer with electrical contact provided via the metallic interconnects of the ASIC. The MEMS structures can also be made of metallic alloys, conductive oxides and amorphous semiconductors. The integrated capping, which provides a sealed cavity, is accomplished through bonding pads defined in the post-processing of the CMOS substrate.

Claims

1. A method, comprising:

forming a CMOS ASIC with ASIC interconnect layers including a last interconnect layer with last metallic interconnects to receive MEMS device input signals, contact pads for ASIC processed output signals, and a cap pad;

depositing a first mold layer on the last interconnect layer;

forming a first lithographic pattern on the first mold layer;

etching the first lithographic pattern to form a first etched surface with MEMS anchor windows exposing the last metallic interconnects and first cap sidewall windows exposing the cap pad;

electroplating copper on the first etched surface to form a first electroplated copper surface;

planarizing the first electroplated copper surface to the first mold layer to render electroplated copper anchor structures in the MEMS anchor windows and a first cap sidewall structure in the first cap sidewall windows, wherein the electroplated copper anchor structures in the MEMS anchor windows contact the last metallic interconnects to receive the MEMS device input signals and the first cap sidewall structure is in contact with the cap pad;

depositing a second mold layer on the first mold layer;

forming a second lithographic pattern on the second mold layer;

etching the second lithographic pattern to form a second etched surface with first MEMS feature windows and second cap sidewall windows;

electroplating copper on the second etched surface to form a second electroplated copper surface;

planarizing the second electroplated copper surface to the second mold layer to expose electroplated copper MEMS features and a second cap sidewall structure, such that the electroplated copper MEMS features reside within the first cap sidewall structure and the second cap sidewall structure;

depositing a third mold layer on the second mold layer;

forming a third lithographic pattern on the third mold layer;

etching the third lithographic pattern to form a third etched surface with third cap sidewall windows;

electroplating copper on the third etched surface to form a third electroplated copper surface;

planarizing the third electroplated copper surface to the third mold layer to render a third cap sidewall structure;

depositing a fourth mold layer on the third mold layer;

forming a fourth lithographic pattern on the fourth mold layer;

etching the fourth lithographic pattern to form a fourth etched surface with a cap ceiling window;

electroplating copper on the fourth etched surface to form a fourth electroplated copper surface; and

planarizing the fourth electroplated copper surface to render a cap ceiling enclosing the electroplated copper MEMS structure features.

2. The method of claim 1 further comprising depositing a protective layer on the first etched surface.

3. The method of claim 2 wherein the protective layer is selected from TiN, TaN, MN, Pt, Ru, Ti, W, Ta, In₂O₃, SnO₂ and Indium-Tin-Oxide.

4. The method of claim 2 wherein the protective layer is up to 1000 nanometers thick.

5. The method of claim 1 further comprising depositing a protective film on the electroplated copper MEMS features.

6. The method of claim 5 wherein the protective film is a metal oxide.

7. The method of claim 6 wherein the metal oxide is selected from Ta₂O₅, In₂O₃, SnO₂, Indium-Tin-Oxide, TiO₂, SiO₂, Y₂O₃, Al₂O₃, HfO₂, ZrO₂, ZrSiO₄, BaTiO₃, and BaZrO₃.

8. The method of claim 5 wherein the protective film is deposited using one of atomic layer deposition, chemical vapor deposition and physical vapor deposition.

9. The method of claim 5 wherein the protective film is operative to prevent corrosion and diffusion of electroplated copper during the processing and operation of the electroplated copper MEMS features.

10. The method of claim 1 wherein the cap ceiling has at least one hole to facilitate processing of features beneath the cap ceiling.

11. The method of claim 10 further comprising sealing the at least one hole to form a sealed cavity.

12. The method of claim 11 wherein sealing is performed using PVD, CVD electro deposition or electro-less deposition.

13. The method of claim 11 wherein sealing is performed using a material selected from semiconductors, metals, metal alloys, metal oxides and dielectrics, including, but not limited to Cu, Al, Ag, W, Pt, Pd, Ru, Co, Cd, Pb, Zn, Cadium Zinc Telluride (CZT), HfB₂, In₂O₃, SnO₂, Indium Tin Oxide (ITO) or a combination thereof.

14. The method of claim 11 wherein pressure in the sealed cavity is determined by the pressure at which sealing is performed.

15. The method of claim 1 further comprising accessing the last interconnect layer by back etching.

16. The method of claim 15 wherein back etching is selected from deep reactive ion etching, reactive ion etching, and wet etching in KOH or TMAH-based solutions.