Semiconductor device including leadframe with a combination of leads and lands and method

• US 9,631,481 B1
• Filed: 10/14/2016
• Issued: 04/25/2017
• Est. Priority Date: 01/27/2011
• Status: Active Grant

• Current Assignee: Amkor Technology Singapore Holding Pte., Ltd. (Amkor Technology Incorporated)
• Original Assignee: Amkor Technology Incorporated
• Inventors: Bae, Jae Min, Kim, Byong Jin, Bang, Won Bae
• Primary Examiner(s): Smoot, Stephen W
• Assistant Examiner(s): Chin, Edward
• Application Number:
  US15/293,524
• Time in Patent Office: 193 Days
• CPC Class Codes: C08G 77/14 containing silicon bound to oxygen-containing groups C08G77/045 takes precedence
• CPC Class Codes: C08L 2205/025 containing two or more polymers of the same hierarchy C08L, and differing only in parameters such as density, comonomer content, molecular weight, structure
• CPC Class Codes: C08L 83/00 Compositions of macromolecular compounds obtained by reactions forming in the main chain of the macromolecule a linkage containing silicon with or without sulfur, nitrogen, oxygen or carbon only; Compositions of derivatives of such polymers
• CPC Class Codes: C08L 83/06 containing silicon bound to oxygen-containing groups C08L83/12 takes precedence
• CPC Class Codes: E21B 47/107 using acoustic means
• CPC Class Codes: E21B 49/005 Testing the nature of borehole walls or the formation by using drilling mud or cutting data
• CPC Class Codes: G01N 29/024 by measuring propagation velocity or propagation time of acoustic waves
• CPC Class Codes: H01L 21/4825 Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/32245 the item being metallic
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/3114 the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49513 having bonding material between chip and die pad
• CPC Class Codes: H01L 23/4952 the additional leads being a bump or a wire
• CPC Class Codes: H01L 23/49548 Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/564 Details not otherwise provided for, e.g. protection against moisture getters H01L23/26
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 33/56 : Materials, e.g. epoxy or silicone resin

Abstract

A semiconductor device includes a die pad, a plurality of first lands each having a first land first top recessed portion disposed on a first land first end distal to the die pad, and a plurality of second lands each having a second land first bottom recessed portion disposed on a second land first end distal to the die pad. A semiconductor die is electrically connected to the first and second lands. A package body, which defines a bottom surface and a side surface, at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body.

Claims

1. A semiconductor device, comprising:

a die pad;

a plurality of first lands in spaced relation to the die pad, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad, and wherein each of the first lands has a first land second top recessed portion disposed on a first land second end proximate to the die pad;

a plurality of second lands in spaced relation to the die pad, wherein each of the second lands has a second land first bottom recessed portion disposed on a second land first end distal to the die pad;

a semiconductor die electrically coupled to the first and second lands; and

a package body defining a bottom surface and a side surface, the package body at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in and substantially flush with the bottom surface of the package body, wherein;

the first and second lands are positioned between the die pad and the side surface;

the second lands are positioned proximate to the side surface;

the first lands are positioned between the die pad and the second lands; and

the first land first recessed top portion of each first land and the second land first bottom recessed portion of each second land are encapsulated by the package body.

2. The semiconductor device of claim 1, wherein each of the second lands has a second land second bottom recessed portion disposed on a second land second end proximate to the die pad.

3. The semiconductor device of claim 1, wherein:

the die pad has multiple peripheral edge segments;

the semiconductor die is coupled to the die pad;

the plurality of first lands are segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad;

the plurality of second lands are segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad; and

the semiconductor device further comprises a plurality of third lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein;

each of the third lands has a third land first top recessed portion disposed on a third land first end proximate to the die pad; and

the third land first top recessed portion of each third land is encapsulated by the package body.

4. The semiconductor device of claim 3, wherein the first lands are separated from the third lands by at least one trench formed in the bottom surface of the package body.

5. The semiconductor device of claim 3 further comprising:

a plurality of fourth lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the die pad in spaced relation thereto, wherein;

each of the fourth lands has a fourth land first bottom recessed portion disposed on a fourth land first end distal to the die pad; and

the fourth lands are generally concentrically positioned between the second lands and the third lands.

6. The semiconductor device of claim 5, wherein each of the fourth lands has a fourth land second bottom recessed portion disposed on fourth land second end proximate to the die pad.

7. The semiconductor device of claim 3, wherein:

the first lands are generally concentrically positioned between the third lands and the die pad such that each set of the first lands extends along a corresponding set of the third lands; and

the third lands are generally concentrically positioned between the second lands and the first lands such that each set of the third lands extends along a corresponding set of the second lands.

8. The semiconductor device of claim 7, wherein the first lands of each set thereof are offset relative to the third lands of the corresponding set thereof.

9. The semiconductor device of claim 1 further comprising:

a tie bar comprising an inner portion and an outer portion separated from the inner portion by a gap, the inner portion attached to and extending from the die pad, the tie bar having a tie bar top surface and a tie bar bottom surface, wherein;

the tie bar top surface of the outer portion is co-planar with the die pad top surface;

a first portion of the tie bar bottom surface of the outer portion comprises a recessed surface that is half-etched; and

the first portion of the tie bar bottom surface is encapsulated by the package body.

10. The semiconductor device of claim 9, wherein:

the die pad has a generally quadrangular configuration;

the first and second lands are segregated into at least four sets that each extend along a respective one of the peripheral edge segments of the die pad; and

a second portion of the tie bar bottom surface is co-planar with the die pad bottom surface and exposed in and substantially flush with the bottom surface of the package body.

11. The semiconductor device of claim 1, wherein a portion of the die pad is exposed in and substantially flush with the bottom surface of the package body.

12. The semiconductor device of claim 1, wherein the semiconductor die is electrically connected to the first and second lands by conductive wires which are covered by the package body.

13. A semiconductor device, comprising:

a generally planar die pad;

a plurality of first lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad;

a plurality of second lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the second lands has a second land first bottom recessed portion disposed on a second land first end distal to the die pad;

a semiconductor die electrically coupled to the first and second lands; and

a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first and second lands and the semiconductor die such that at least portions of the first and second lands are exposed in the bottom surface of the package body, wherein;

the first and second lands are positioned between the die pad and the side surface of the package body;

the second lands are positioned proximate to the side surface;

the first lands are positioned between the die pad and the second lands such that no portion of the first lands are positioned proximate to the side surface; and

the first land first recessed portion of each first land and the second land first bottom recessed portion of each second land are encapsulated by the package body.

14. The semiconductor device of claim 13 further comprising:

a plurality of third lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein each of the third lands has a third land first top recessed portion disposed on a third land first end proximate to the die pad, wherein;

the third land first top recessed portion of each third land is encapsulated by the package body;

the semiconductor die is electrically coupled to the third lands; and

the first lands are generally concentrically positioned between the third lands and the die pad, and the third lands are generally concentrically positioned between the second lands and the first lands.

15. The semiconductor device of claim 14, wherein:

each of the first lands has a first land second top recessed portion disposed on a first land second end proximate to the die pad; and

each of the second lands has a second land second bottom recessed portion disposed on a second land second end proximate to the die pad.

16. The semiconductor device of claim 14 further comprising:

a plurality of fourth lands extending along peripheral edge segments of the die pad in spaced relation thereto, wherein;

each of the fourth lands has a fourth land first bottom recessed portion disposed on a fourth land first end distal to the die pad; and

the fourth lands are generally concentrically positioned between the second lands and the third lands.

17. The semiconductor device of claim 16, wherein each of the fourth lands has a fourth land second bottom recessed portion disposed on fourth land second end proximate to the die pad.

18. The semiconductor device of claim 17, wherein:

the plurality of first lands and the plurality of third are offset relative to each other; and

the plurality of second lands and the plurality of fourth lands are offset relative to each other.

19. The semiconductor device of claim 13 further comprising:

a tie bar comprising an inner linear portion and an outer linear portion separated from the inner linear portion by a gap, wherein;

the inner linear portion is attached to and extends from the die pad,

the outer linear portion has a bottom surface with a first portion that is generally co-planar to a bottom surface of the die pad and a second portion that is recessed such that the second portion is recessed relative to the first portion; and

the second portion of the bottom surface of the tie bar is encapsulated by the package body.

20. A semiconductor device, comprising:

a semiconductor die defining multiple peripheral edge segments;

a plurality of first lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the semiconductor die, wherein each of the first lands has a first land first top recessed portion disposed on a first land first end distal to the die pad;

a plurality of second lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the semiconductor die, wherein each of the second lands has a second land first top recessed portion disposed on a second land first end proximate to the die pad;

a plurality of third lands segregated into at least two sets extending along respective ones of at least two peripheral edge segments of the semiconductor die, wherein each of the third lands has a third land first bottom recessed portion disposed on a third land first end distal to the die pad; and

a package body defining a generally planar bottom surface and a side surface, the package body at least partially encapsulating the first, second, and third lands and the semiconductor die such that at least portions of the first, second, and third lands are exposed in and substantially flush with the bottom surface of the package body, wherein;

the semiconductor die is electrically coupled to the first, second, and third lands;

at least the second and third lands are positioned between the semiconductor die and the side surface of the package body; and

the first land first recessed portion of each first land, the second land first top recessed portion of each second land, and the third land first bottom recessed portion of each third land are encapsulated by the package body.