Methods, apparatus, and systems for contacting semiconductor dies that are electrically coupled to test access interface positioned in scribe lines of a wafer
First Claim
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1. A device, comprising:
- a first wafer having i) a first plurality of semiconductor dies, ii) a first plurality of scribe lines, each of the first plurality of scribe lines adjacent one or more of the first plurality of semiconductor dies, iii) a first test access interface positioned in one or more of the first plurality of scribe lines, the first test access interface having a first plurality of through-substrate conductors with a standardized physical layout, wherein the through-substrate conductors comprise a ground line and a signal line, and iv) electrical couplings between at least some of the first plurality of through-substrate conductors and at least one of the first plurality of semiconductor dies.
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Abstract
A semiconductor device includes a first wafer having i) a plurality of semiconductor dies, ii) a plurality of scribe lines adjacent one or more of the semiconductor dies, iii) a test access interface positioned in one or more of the scribe lines, wherein the test access interface has a first plurality of through-substrate conductors with a standardized physical layout, and iv) electrical couplings between at least some of the through-substrate conductors and at least one of the semiconductor dies. Methods, apparatus and systems for testing this and other types of semiconductor devices are also disclosed.
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Citations
19 Claims
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1. A device, comprising:
a first wafer having i) a first plurality of semiconductor dies, ii) a first plurality of scribe lines, each of the first plurality of scribe lines adjacent one or more of the first plurality of semiconductor dies, iii) a first test access interface positioned in one or more of the first plurality of scribe lines, the first test access interface having a first plurality of through-substrate conductors with a standardized physical layout, wherein the through-substrate conductors comprise a ground line and a signal line, and iv) electrical couplings between at least some of the first plurality of through-substrate conductors and at least one of the first plurality of semiconductor dies. - View Dependent Claims (2, 3, 4, 5)
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6. A method for laying out elements on a wafer, comprising:
- using a computer,
electronically specifying positions of a plurality of semiconductor dies on the wafer, the positions of the semiconductor dies defining scribe lines adjacent the semiconductor dies; electronically selecting a test access interface from among a plurality of test access interfaces, the selected test access interface having a standardized physical layout that is independent of a physical layout of the semiconductor dies on the wafer; electronically specifying a position of an instance of the selected test access interface with respect to the physical layout of the semiconductor dies on the wafer, the position causing the instance of the selected test access interface to be located in one or more of the scribe lines; and electronically specifying a plurality of electrical couplings between the instance of the selected test access interface and at least one of the semiconductor dies. - View Dependent Claims (7, 8)
- using a computer,
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9. Apparatus for contacting semiconductor dies during semiconductor test, the apparatus comprising:
a substrate having a first surface, a second surface opposite the first surface, a plurality of through-substrate conductors extending between the first surface and the second surface, a redistribution layer on the second surface and having electrical connections to the through-substrate conductors, and a plurality of probe sets coupled to the first surface, wherein each probe set has a standardized physical layout for contacting a corresponding scribe line test access interface on a wafer, each of the plurality of probe sets has a position with respect to the first substrate corresponding to a position of at least one scribe line on the wafer, and each of a number of probes in the probe sets is coupled to a respective one of the through-substrate conductors. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for contacting semiconductor dies during semiconductor test, the method comprising:
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providing a wafer having a plurality of semiconductor dies, a plurality of scribe lines, and at least one test access interface, wherein each of the at least one test access interface has a plurality of through-substrate conductors that are electrically coupled to at least one of the semiconductor dies, and wherein the wafer has at least one pair of through-substrate conductors that are electrically coupled; contacting the wafer with a space transformer having a substrate having a first surface, a second surface opposite the first surface, a plurality of through-substrate conductors extending between the first surface and the second surface, a first pad on the second surface connected to the through-substrate conductors, a redistribution layer on the second surface and having an electrical connection that connects a second pad on the second surface to the through-substrate conductors, the first pad and the second pad for contacting a probe head, and at least one probe set for contacting one or more of the at least one test access interface; and verifying an alignment between the at least one probe set and the one or more of the at least one test access interface by performing a DC continuity loopback test using at least one pair of probes extending from the space transformer and the at least one pair of through-substrate conductors that are electrically coupled.
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19. Apparatus for contacting semiconductor dies during semiconductor test, the apparatus comprising:
a plurality of probe heads, each of the probe heads having at least one probe set with a standardized physical layout for contacting a plurality of through-semiconductor conductors in a corresponding scribe line test access interface on a wafer, each of the probe heads individually controlled by programmed robotics to contact a respective test access interface on the wafer.
Specification