System on chip method thereof, and device including the same

• US 9,632,567 B2
• Filed: 02/24/2015
• Issued: 04/25/2017
• Est. Priority Date: 03/28/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jong Lae, Lee, Woo Jin, Park, Sang Il, Lee, Gyeong Teak
• Primary Examiner(s): Tran, Vincent
• Application Number:
  US14/630,015
• Publication Number:
  US 20150277534A1
• Time in Patent Office: 791 Days
• CPC Class Codes: G06F 1/163 Wearable computers, e.g. on a belt
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising of a scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time; monitoring operating frequency of the target device; and selectively deferring execution of DVFS at a later scheduled time based on the operating frequency of the target device; wherein execution of DVFS at a next scheduled time is deferred when the operating frequency of the target device is below a given minimum frequency.

Claims

1. A Dynamic Voltage and Frequency Scaling (DVFS) method, comprising:

scheduling execution of DVFS to adjust frequency or voltage of a target device at a first scheduled time;

monitoring operating frequency of the target device; and

deferring execution of DVFS at a second scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is below a minimum frequency and a central processing unit (CPU) is in an idle state.

2. The method of claim 1, further comprising executing DVFS at a third scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is greater than the minimum frequency and the CPU is in a run state.

3. The method of claim 1, further comprising executing DVFS at a third scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is greater than the minimum frequency and the CPU is in the idle state.

4. The method of claim 1, wherein the CPU is forced from the idle state to a run state in response to an interrupt to execute DVFS at a third scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is above the minimum frequency.

5. The method of claim 1, wherein the target device is a memory interface.

6. The method of claim 1, wherein the operating frequency or a supplied voltage of the target device is reduced upon execution of DVFS.

7. A system on chip (SOC), comprising:

a central processing unit (CPU), a memory, and a target device controlled by the CPU, the memory having stored instructions executable by the CPU to;

schedule dynamic voltage and frequency sealing (DVFS) to adjust frequency or voltage of the target device at a first scheduled time;

receive operating frequency of the target device; and

defer execution of DVFS at a second scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is below a minimum frequency and the CPU is in an idle state.

8. The SOC of claim 7, wherein the CPU is forced from the idle state to a run state to execute DVFS in response to an interrupt when the operating frequency of the target device is above the minimum frequency.

9. The SOC of claim 7, wherein the CPU is not forced from the idle state to the run state in response to an interrupt to execute DVFS at a third scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is below the minimum frequency.

10. The SOC of claim 7, wherein the target device is a memory interface.

11. The SOC of claim 7, wherein the target device is a non-CPU intellectual property (IP).

12. The Soc of claim 11, wherein the second target device is an input/output (I/O) interface.

13. The SOC of claim 7, further including a second target device controlled by the CPU, wherein the memory includes further stored instructions executable by the CPU to perform DVFS to adjust frequency or voltage of the second target device.

14. The Soc of claim 7, wherein the operating frequency or a supplied voltage of the target device is reduced upon execution of DVFS.

15. The Soc of claim 7, wherein the Soc is embodied in of a smartphone, a camera, a wearable smart device, or an internet of things (IoT).

16. A wearable electronic device, comprising:

a system on Chip (SOC), comprising;

a central processing unit (CPU), a memory, and a memory interface controlled by the CPU, the memory having stored instructions executable by the CPU to;

schedule dynamic voltage and frequency scaling (DVFS) to adjust frequency or voltage of a target device at a first scheduled time;

receive operating frequency of the target device; and

defer execution of DVFS at a second scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is below a minimum frequency and the CPU is in an idle state;

a memory device connected to the memory interface; and

a display.

17. The wearable electronic device of claim 16, wherein the CPU is forced from the idle state to the run state to execute DVFS in response to an interrupt when the operating frequency of the target device is above the minimum frequency.

18. The wearable electronic device of claim 16, wherein the CPU is not forced from the idle state to the run state in response to an interrupt to execute DVFS at a third scheduled time, which occurs after the first scheduled time, when the operating frequency of the target device is below the minimum frequency.

19. The wearable electronic device of claim 16, wherein the target device is a memory interface.

20. The wearable electronic device of claim 16, wherein the target device is a non-CPU intellectual property (IP).