Systems and methods for identifying storage resources that are not in use

• US 9,632,727 B2
• Filed: 06/19/2014
• Issued: 04/25/2017
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: Unification Technologies LLC (Acacia Research Corporation)
• Original Assignee: Longitude Enterprise Flash S.à r.l. (Vector Capital Corporation)
• Inventors: Flynn, David, Thatcher, Jonathan, Zappe, Michael
• Primary Examiner(s): DUDEK JR, EDWARD J
• Application Number:
  US14/309,751
• Publication Number:
  US 20140372679A1
• Time in Patent Office: 1,041 Days
• CPC Class Codes: G06F 1/183 Internal mounting support structures, e.g. for printed circuit boards, internal connecting means for buses G06F13/409
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0804 with main memory updating G06F12/0806 takes precedence
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 12/121 using replacement algorithms
• CPC Class Codes: G06F 12/123 with age lists, e.g. queue, most recently used [MRU] list or least recently used [LRU] list
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 13/426 using an embedded synchronisation, e.g. Firewire bus, Fibre Channel bus, SSA bus
• CPC Class Codes: G06F 2211/002 Bus
• CPC Class Codes: G06F 2211/103 Hybrid, i.e. RAID systems with parity comprising a mix of RAID types
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/222 Non-volatile memory
• CPC Class Codes: G06F 2212/70 Details relating to dynamic memory management
• CPC Class Codes: G06F 2212/7203 Temporary buffering, e.g. using volatile buffer or dedicated buffer blocks
• CPC Class Codes: G06F 2212/7205 Cleaning, compaction, garbage collection, erase control
• CPC Class Codes: G06F 2212/7208 : Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G06F 3/0604 : Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0608 : Saving storage space on storage systems
• CPC Class Codes: G06F 3/0613 : in relation to throughput
• CPC Class Codes: G06F 3/0619 : in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0643 : Management of files
• CPC Class Codes: G06F 3/065 : Replication mechanisms
• CPC Class Codes: G06F 3/0652 : Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0656 : Data buffering arrangements
• CPC Class Codes: G06F 3/0659 : Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 : Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 : Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• CPC Class Codes: G06F 3/0688 : Non-volatile semiconductor memory arrays
• CPC Class Codes: G06F 9/52 : Program synchronisation; Mutual exclusion, e.g. by means of semaphores
• CPC Class Codes: G06F 9/54 : Interprogram communication
• CPC Class Codes: H04L 67/02 : based on web technology, e.g. hypertext transfer protocol [HTTP]
• CPC Class Codes: H04L 67/1097 : for distributed storage of data in networks, e.g. transport arrangements for network file system [NFS], storage area networks [SAN] or network attached storage [NAS]
• CPC Class Codes: H05K 7/1444 : Complex or three-dimensional-arrangements; Stepped or dual mother boards
• CPC Class Codes: H05K 7/1487 : Blade assemblies, e.g. blade cases or inner arrangements within a blade
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An apparatus, system, and method are disclosed for managing a non-volatile storage medium. A storage controller receives a message that identifies data that no longer needs to be retained on the non-volatile storage medium. The data may be identified using a logical identifier. The message may comprise a hint, directive, or other indication that the data has been erased and/or deleted. In response to the message, the storage controller records an indication that the contents of a physical storage location and/or physical address associated with the logical identifier do not need to be preserved on the non-volatile storage medium.

Claims

1. An apparatus, comprising:

a solid-state storage medium;

a solid-state storage controller configured to implement storage operations on the solid state storage medium in response to requests from a computer system, including storing data pertaining to logical addresses of a logical address space at respective physical addresses of the solid-state storage medium; and

an indexer, comprised within the solid-state storage controller, wherein the indexer is configured to assign logical addresses of the logical address space to physical addresses in use to store data pertaining to the logical addresses on the solid-state storage medium;

wherein the indexer is further configured to remove an assignment between an identified logical address and a physical address of the solid-state storage medium in response to a message received from a host operating system, the message indicating that the identified logical address is erased.

2. The apparatus of claim 1, wherein the indexer assigns logical addresses to physical addresses by use of index entries, and wherein the indexer removes an index entry corresponding to the identified logical address in response to the message.

3. The apparatus of claim 1, wherein the indexer assigns logical addresses to physical addresses by use of index metadata maintained in a memory of the storage controller.

4. The apparatus of claim 1, wherein the indexer comprises firmware of the solid-state storage controller.

5. The apparatus of claim 1, further comprising a garbage collector configured to designate that the physical address previously assigned to the identified logical address comprises data suitable for removal from the solid-state storage medium in response to the message.

6. The apparatus of claim 1, wherein the solid-state storage controller comprises a bus interface configured to communicatively couple the solid-state storage controller to the computer system, wherein the bus interface comprises one of a universal serial bus interface, an Institute of Electrical and Electronics Engineers 1394 bus interface, an external Serial Advanced Technology Attachment bus interface, a Peripheral Component Interconnect (PCI) bus interface, a PCI Express bus interface, an InfiniBand interface, an Integrated Drive Electronics (IDE) bus interface, an AT Attachment (ATA) interface, a Parallel ATA (PATA) interface, a Serial ATA (SATA) bus interface, an external SATA bus interface, a Small Computer System Interface (SCSI) bus interface, an internet SCSI interface, and a Fibre Channel interface.

7. A system, comprising:

means for controlling a solid-state storage medium, comprising,

means for storing data referenced by logical blocks of a logical address space on physical storage blocks of the solid-state storage medium, and

means for maintaining logical-to-physical mappings between the logical blocks of the logical address space and physical storage blocks storing data referenced by the respective logical blocks on the solid-state storage medium; and

means for receiving a message from a storage client that identifies a logical block that is not being used to reference data stored on the solid-state storage medium, wherein the logical block is mapped to a particular physical storage block on the solid-state storage medium by the logical-to-physical mappings; and

wherein the means for controlling the solid-state storage medium further comprise means for unmapping the identified logical block from the particular physical storage block in the logical-to-physical mappings.

8. The system of claim 7, further comprising means for providing a storage interface to accept requests to perform storage operations on the solid-state storage medium in reference to the logical blocks and to accept the message identifying the logical block that is not being used to reference data stored on the solid-state storage medium.

9. The system of claim 7, wherein unmapping the identified logical block comprises invalidating an entry of the logical-to-physical mappings, the entry indicating a mapping between the identified logical block and the particular storage block.

10. The system of claim 7, further comprising means for indicating that data stored on the particular physical storage block can be erased from the solid-state storage medium.

11. The system of claim 7, further comprising means for recording that the identified logical block is unmapped on the solid-state storage medium.

12. A non-volatile solid-state storage system, comprising:

a storage interface configured to communicate with a storage client;

a storage processor coupled to the storage interface;

a flash memory device coupled to the storage processor; and

a logical-to-physical translation layer maintained by the storage processor, wherein the logical-to-physical translation layer maps logical block addresses to corresponding respective physical block addresses of the flash memory device, wherein the storage processor is configured to;

receive, from the storage client through the storage interface, an empty-block directive command and a range of logical block addresses,

update the logical-to-physical translation layer to indicate that data stored in physical block addresses corresponding to the received logical block addresses do not need to be preserved, and

store persistent data on the flash memory device, the persistent data indicating that the data corresponding to the received logical block addresses is deleted at the storage client.

13. The system of claim 12, wherein the logical-to-physical translation layer is stored in the flash memory device.

14. The system of claim 12, further comprising a volatile memory device coupled to the storage processor, wherein the logical-to-physical translation layer is stored in the volatile memory device.

15. The system of claim 12 wherein the storage processer is configured such that, responsive to receiving a read request specifying one or more logical addresses included in the empty-block directive command, the storage processor returns a predetermined data string.

16. The system of claim 15, wherein data bits of the predetermined data string have a uniform logic level.