Storage compute device with tiered memory processing

• US 9,632,729 B2
• Filed: 05/05/2015
• Issued: 04/25/2017
• Est. Priority Date: 05/07/2014
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Li, Peng, Bohn, Richard Esten, Tetzlaff, David, Gomez, Kevin Arthur
• Primary Examiner(s): Mackall, Larry
• Application Number:
  US14/704,111
• Publication Number:
  US 20150324125A1
• Time in Patent Office: 721 Days
• CPC Class Codes: G06F 2206/1014 One time programmable [OTP] memory, e.g. PROM, WORM
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0631 by allocating resources to storage systems
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0685 Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays

Abstract

A data object is received at a storage compute device in response to a request from a host. A requirement of the data object is determined based on a computation to be performed on the data object. The requirement related to at least speed and capacity of media used to store the data object. A tier is selected from the storage compute device based on speed and capacity characteristics of the selected tier corresponding to the requirement of the data object. The data object is stored in the selected tier.

Claims

1. A method comprising:

receiving a data object and a command at a storage compute device in response to a request from a host, the command specifying a matrix computation to be performed on the data object at the storage compute device;

determining a requirement of the data object based on the matrix computation, the requirement related to at least speed and capacity of media used to store the data object;

selecting a tier of non-volatile memory from a plurality of tiers of the storage compute device based on speed and capacity characteristics of the selected tier corresponding to the requirement of the data object;

storing the data object in the selected tier; and

performing the matrix computation on the data object stored in the selected tier.

2. The method of claim 1, further comprising separating the data object into two data sub-objects and storing the two data sub-objects in two different tiers based on the computation being performed on the data object.

3. The method of claim 2, wherein the sub-objects comprise a matrix and a transformed version of the matrix or metadata describing the matrix.

4. The method of claim 2, wherein the sub-objects comprise a matrix formatted using different types of compression.

5. The method of claim 1, wherein the requirement further is further related to reliability of the media used to store the data object.

6. The method of claim 1, wherein the matrix computation produces an intermediate result, and wherein the intermediate result is stored in a different tier than the data object.

7. The method of claim 1, wherein tiers of the storage compute device further comprise volatile memory.

8. The method of claim 7, further comprising performing the matrix computation in a second selected tier of the volatile memory using the stored data object.

9. The method of claim 7, further comprising performing the matrix computation within the selected tier using the stored data object, wherein the computation produces an intermediate result, the intermediate result being stored in a second selected tier of the volatile memory.

10. The method of claim 1, wherein the matrix computation involves the data object and a second data object received at the storage compute device in response to the request from the host.

11. The method of claim 1, wherein the requirement is further based on a size of the data object and the ability to retrieve the object using a sequential read operation.

12. A storage compute device, comprising:

a host interface;

a channel interface facilitating access to non-volatile memory, the non-volatile memory comprising a plurality of tiers having different characteristics relating to at least speed and capacity; and

a processor coupled to the host interface and the channel interface, the processor configured to;

receive a data object and a command via the host interface, the command specifying a matrix computation to be performed on the data object at the storage compute device;

determine a requirement of the data object based on the matrix computation, the requirement related to at least speed and capacity of media used to store the data object;

select a tier from the plurality of tiers of based on speed and capacity characteristics of the selected tier corresponding to the requirement of the data object;

store the data object in the selected tier; and

perform the matrix computation on the data object stored in the selected tier.

13. The storage compute device of claim 12, wherein the processor is further configured to separate the data object into two data sub-objects and store the two data sub-objects in two different tiers based on the computation being performed on the data object.

14. The storage compute device of claim 13, wherein the sub-objects comprise a matrix and a transformed version of the matrix.

15. The storage compute device of claim 13, wherein the sub-objects comprise a matrix and metadata describing the matrix.

16. The storage compute device of claim 13, wherein the sub-objects comprise a matrix formatted using different types of compression.

17. The storage compute device of claim 12, wherein the matrix computation produces an intermediate result, and wherein the intermediate result is stored in a different tier than the data object.

18. The storage compute device of claim 12, wherein the plurality of tiers each comprise separate processing resources coupled to respective media in each of the tiers, the processing resources are configured to reduce performance gaps between adjacent tiers or to reduce power consumption of the storage compute device.

19. A storage compute device, comprising:

a host interface;

a non-volatile memory comprising a plurality of tiers, each of the tiers comprising;

media having specific characteristics relating to at least speed and capacity; and

a processing resource coupled to media, the processing resource configured to reduce performance gaps between adjacent ones of the plurality of tiers;

a processor coupled to the host interface and the non-volatile memory, the processor configured to;

receive a data object and a command via the host interface, the command specifying a matrix computation to be performed on the data object at the storage compute device;

select a tier from the plurality of tiers of based on speed and capacity characteristics of the selected tier corresponding to a requirement of the data object;

store the data object in the selected tier; and

perform the matrix computation on the data object stored in the selected tier.

20. The storage compute device of claim 19, wherein the processing resources are configured to reduce the performance gaps between adjacent ones of the plurality of tiers by configuring at least two tiers to have different configurations related to one or more of clock speed, bus speed, word size, and memory buffer size.