Data storage device and flash memory control method
First Claim
1. A data storage device, comprising:
- a flash memory, divided into a plurality of blocks with each block comprising a plurality of pages; and
a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory,wherein;
the microcontroller is configured to allocate the flash memory to provide a first run-time write block from the blocks;
between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with a first section of physical-to-logical information while a second section of physical-to-logical information is waiting to be updated to the logical-to-physical address mapping table in a time interval between another pair of write operations performed on the first run-time write block;
the logical-to-physical address mapping table is provided within the flash memory; and
a first physical-to-logical address mapping table that provides the first and second sections of physical-to-logical information is established in the random access memory to record logical addresses corresponding to physical addresses of one block.
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Accused Products
Abstract
A data storage device with flash memory and a flash memory control method are disclosed, which upload the physical-to-logical address mapping information of one block to the flash memory section by section. A microcontroller is configured to allocate a flash memory to provide a first run-time write block. Between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with just part of a first physical-to-logical address mapping table. The logical-to-physical address mapping table is provided within the flash memory. The first physical-to-logical address mapping table is established in the random access memory to record logical addresses corresponding to physical addresses of one block.
44 Citations
16 Claims
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1. A data storage device, comprising:
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a flash memory, divided into a plurality of blocks with each block comprising a plurality of pages; and a control unit, coupling the flash memory to a host and comprising a microcontroller and a random access memory, wherein; the microcontroller is configured to allocate the flash memory to provide a first run-time write block from the blocks; between a first write operation and a second write operation of the first run-time write block, the microcontroller updates a logical-to-physical address mapping table in accordance with a first section of physical-to-logical information while a second section of physical-to-logical information is waiting to be updated to the logical-to-physical address mapping table in a time interval between another pair of write operations performed on the first run-time write block; the logical-to-physical address mapping table is provided within the flash memory; and a first physical-to-logical address mapping table that provides the first and second sections of physical-to-logical information is established in the random access memory to record logical addresses corresponding to physical addresses of one block. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A flash memory control method, comprising:
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allocating a flash memory to provide a first run-time write block from a plurality of blocks of the flash memory, each block comprising a plurality of pages; and between a first write operation and a second write operation of the first run-time write block, updating a logical-to-physical address mapping table in accordance with a first section of physical-to-logical information while a second section of physical-to-logical information is waiting to be updated to the logical-to-physical address mapping table in a time interval between another pair of write operations performed on the first run-time write block, wherein; the logical-to-physical address mapping table is provided within the flash memory; and a first physical-to-logical address mapping table that provides the first and second sections of physical-to-logical information is established in the random access memory to record logical addresses corresponding to physical addresses of one block. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16)
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Specification