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Segmentation of blocks for faster bit line settling/recovery in non-volatile memory devices

  • US 9,633,742 B2
  • Filed: 07/10/2014
  • Issued: 04/25/2017
  • Est. Priority Date: 07/10/2014
  • Status: Active Grant
First Claim
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1. A non-volatile memory circuit, comprising:

  • an array of non-volatile memory cells formed as a plurality of blocks;

    a plurality of bit lines spanning the plurality of blocks to which the memory cells of the blocks are connected; and

    sensing circuitry connected to the array, including a plurality of sense amp circuits connected to the bit lines, wherein the sensing circuitry varies a time allotted for biasing the array for a sensing operation of selected memory cells based upon a physical distance along the bit lines from the sense amp circuits to the block of the selected memory cells,wherein;

    each of the blocks belongs to one of a plurality of block groups,each of the block groups contains one or more adjacent blocks of the array,the blocks of a group use a shared time allotment for biasing the array for the sensing operations of selected memory cells belonging thereto,the different block groups use different time allotments for biasing the array for the sensing operations of selected memory cells belonging thereto, andblock groups that are physically closer to corresponding ones of the sense amp circuits along the bit lines than others of the block groups are biased for shorter time allotments than the others of the block groups to reduce total power expended during the biasing.

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