Method for through silicon via structure

• US 9,633,900 B2
• Filed: 02/26/2016
• Issued: 04/25/2017
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Jeng, Shin-Puu, Chiou, Wen-Chih, Tsai, Fang Wen, Tsai, Chen-Yu
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US15/054,481
• Publication Number:
  US 20160181157A1
• Time in Patent Office: 424 Days
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0391 Forming a passivation layer after forming the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05548 : Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05559 : non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05562 : On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05568 : the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1411 : the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16113 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]

Abstract

A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Claims

1. A method comprising:

forming a through substrate via in a substrate, the substrate comprising a device substrate and metallization layers over a first side of the device substrate, the through substrate via comprising a first conductive material having a sidewall, a protruding end of the through substrate via protruding from a second side of the device substrate, wherein a liner covers the sidewall of the first conductive material from a first end of the first conductive material to a second end of the first conductive material;

forming a first passivation layer over the second side of the device substrate and over the liner, the first passivation layer having a surface that is closer to the device substrate than a protruding end of the through substrate via;

recessing the first passivation layer and the liner to expose the sidewall of the first conductive material, wherein the first passivation layer forms a stair-step pattern; and

forming a second conductive material in contact with the sidewall of the first conductive material.

2. The method of claim 1, wherein forming the second conductive material comprises forming a redistribution layer.

3. The method of claim 1, wherein forming the second conductive material comprises:

forming a glue layer over the through substrate via; and

forming a seed layer over the glue layer.

4. The method of claim 3, wherein the glue layer is titanium.

5. The method of claim 1, further comprising forming a second passivation layer over the second conductive material.

6. The method of claim 5, further comprising forming an opening through the second passivation layer and connecting an external device to the through substrate via through the opening.

7. A method comprising:

forming a liner in an opening in a first side of a substrate;

filling the opening with a first conductive material;

thinning a second side of the substrate to expose the liner;

recessing the substrate such that the first conductive material protrudes from the second side of the substrate;

forming a first passivation layer conformally over the second side of the substrate and the first conductive material, the first passivation layer having a first portion adjacent to the second side of the substrate and a second portion extending along a sidewall of the first conductive material;

recessing the second portion of the first passivation layer and the liner to expose a sidewall of the first conductive material, wherein after recessing the second portion of the first passivation layer and the liner, a distance from the second side of the substrate to a top surface of the second portion of the first passivation layer is greater than a distance from the second side of the substrate to a top surface of the first portion of the first passivation layer; and

forming a second conductive material in physical contact with the sidewall a top surface of the first conductive material, and the first portion of the first passivation layer.

8. The method of claim 7, further comprising forming a first connection between the first conductive material and a first external device disposed on the first side of the substrate, wherein the first external device is bonded on the first side of the substrate in a flip chip configuration.

9. The method of claim 7, further comprising forming a second passivation layer over the second conductive material and the first passivation layer.

10. The method of claim 7, wherein the first passivation layer comprises a dielectric material and the liner comprises the dielectric material.

11. The method of claim 10, wherein the dielectric material comprises silicon nitride.

12. The method of claim 7, wherein forming the second conductive material comprises forming a redistribution layer.

13. The method of claim 7, wherein forming the second conductive material comprises forming a glue layer.

14. A method comprising:

forming a through substrate via extending from a first side of a substrate into the substrate, wherein a liner is interposed between the through substrate via and the substrate, wherein the through substrate via extends through at least one metallization layer adjacent the substrate;

recessing the substrate such that the through substrate via and the liner protrude from a second side of the substrate;

depositing a passivation layer over the through substrate via and the liner, wherein a first portion of the passivation layer contacting the liner extends farther from the substrate than a second portion of the passivation layer at a location between the through substrate via and an adjacent through substrate via;

recessing the first portion of the passivation layer to expose the liner;

recessing the liner to expose the through substrate via such that the liner extends farther from the substrate than the first portion of the passivation layer, wherein recessing the liner is performed in a different step than recessing the first portion of the passivation layer; and

electrically connecting the through substrate via to a first semiconductor device in a flip-chip configuration.

15. The method of claim 14, further comprising forming a conductive material in contact with a sidewall of the through substrate via.

16. The method of claim 15, wherein the conductive material comprises a redistribution layer.

17. The method of claim 14, wherein the passivation layer comprises silicon nitride.

18. The method of claim 14, wherein the first semiconductor device is a semiconductor die.

19. The method of claim 14, further comprising electrically connecting the through substrate via to a second semiconductor device, wherein the through substrate via is interposed between the first semiconductor device and the second semiconductor device.

20. The method of claim 19, wherein the second semiconductor device is a printed circuit board.