TSV formation

• US 9,633,929 B2
• Filed: 11/05/2015
• Issued: 04/25/2017
• Est. Priority Date: 09/30/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yang, Ku-Feng, Jeng, Shin-Puu, Chiou, Wen-Chih
• Primary Examiner(s): Gumedzoe, Peniel M
• Application Number:
  US14/933,583
• Publication Number:
  US 20160056090A1
• Time in Patent Office: 537 Days
• CPC Class Codes: H01L 21/288 from a liquid, e.g. electrolytic deposition
• CPC Class Codes: H01L 21/76838 characterised by the formation and the after-treatment of the conductors etching for patterning the conductors H01L21/3213
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13599 Material
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2224/29599 Material
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

A device includes a substrate having a front side and a backside, the backside being opposite the front side. An isolation layer is disposed on the front side of the substrate, wherein first portions of isolation layer and the substrate are in physical contact. A through substrate via (TSV) extends from the front side to the backside of the substrate. An oxide liner is on a sidewall of the TSV. The oxide liner extends between second portions of the substrate and the isolation layer. A dielectric layer having a metal pad is disposed over the isolation layer on the front side of the substrate. The metal pad and the TSV are formed of a same material.

Claims

1. A device comprising:

a substrate having a front side and a backside, the backside being opposite the front side;

an isolation layer on the front side of the substrate, wherein a first portion of the isolation layer and a first portion of the substrate are in physical contact;

a through substrate via (TSV) extending from the front side to the backside of the substrate;

an oxide liner extending along a sidewall of the TSV, wherein the oxide liner further extends between a second portion of the isolation layer and a second portion of the substrate, and wherein a top surface of the second portion of the isolation layer is non-planar;

a dielectric layer over the isolation layer; and

a metal pad in the dielectric layer over the TSV, wherein the metal pad and the TSV are formed of a same material.

2. The device of claim 1, wherein a surface of the second portion of the substrate is non-planar.

3. The device of claim 1 further comprising:

a first diffusion barrier layer on a sidewall of the TSV; and

a metal line in the dielectric layer and a second diffusion barrier layer on a sidewall of the metal line, wherein the first and the second diffusion barrier layers are substantially conformal.

4. The device of claim 3, wherein a first average thickness of the first diffusion barrier layer is within 5% of a second average thickness of the second diffusion barrier layer.

5. The device of claim 3, wherein a first ratio of a first minimum thickness of the first diffusion barrier layer to a second minimum thickness of the second diffusion barrier layer is between about 0.8 and about 1.2.

6. The device of claim 3, wherein a second ratio of a first maximum thickness of the first diffusion barrier layer to a second maximum thickness of the second diffusion barrier layer is between about 0.8 and about 1.2.

7. The device of claim 3, wherein the metal line has a first width less than about 0.6 micrometers, wherein the TSV has a second width less than about 12 micrometers, and wherein the TSV has an aspect ratio greater than about 4.

8. The device of claim 1, wherein there is no interface between the metal pad and the TSV.

9. A device comprising:

a semiconductor substrate;

an isolation layer over the semiconductor substrate, wherein a surface of the isolation layer contacts a surface of the semiconductor substrate;

a through substrate via (TSV) extending through the semiconductor substrate and the isolation layer;

an oxide liner disposed between sidewalls of the TSV and the semiconductor substrate, wherein the oxide liner extends partially between the surface of the isolation layer and the surface of the semiconductor substrate;

a dielectric layer over the isolation layer;

a metal pad in the dielectric layer and connected to the TSV; and

a metal line in the dielectric layer, wherein bottom surfaces of the metal pad and the metal line are substantially level.

10. The device of claim 9 further comprising an etch-stop layer between the dielectric layer and the isolation layer, wherein the TSV further extends through the isolation layer.

11. The device of claim 9, wherein a portion of the isolation layer extends past a sidewall of the semiconductor substrate and contacts a top surface of the oxide liner.

12. The device of claim 9 further comprising a first diffusion barrier layer on sidewalls of the TSV and the metal pad, wherein the first diffusion barrier layer is disposed between the TSV and the oxide liner.

13. The device of claim 12 further comprising a second diffusion barrier layer on sidewalls of the metal line, wherein the first diffusion barrier layer and the second diffusion barrier layer comprise a same material.

14. The device of claim 13, wherein a first average thickness of the first diffusion barrier layer is within 5% of a second average thickness of the second diffusion barrier layer.

15. The device of claim 13, wherein a first ratio of a first minimum thickness of the first diffusion barrier layer to a second minimum thickness of the second diffusion barrier layer is between about 0.8 and about 1.2, and wherein a second ration of a first maximum thickness of the first diffusion barrier layer to a second maximum thickness of the second diffusion barrier layer is between about 0.8 and about 1.2.

16. A device comprising:

a semiconductor substrate;

an isolation layer disposed on a top surface of the semiconductor substrate;

a dielectric layer over the isolation layer;

a conductive feature extending continuously from a bottom surface of the semiconductor substrate to a top surface if the dielectric layer, wherein a first portion of the conductive feature in the semiconductor substrate is narrower than a second portion of the conductive feature in the dielectric layer, and wherein the conductive feature has a substantially same material composition along a line extending through the conductive feature and perpendicular to the top surface of the semiconductor substrate;

a first diffusion barrier layer on sidewalls of the conductive feature;

a metal line in the dielectric layer, wherein bottom surfaces of the metal line and the second portion of the conductive feature are substantially leveled;

a second diffusion barrier layer on sidewalls and a bottom surface of the metal line, wherein the first diffusion barrier layer and the second diffusion barrier layer comprise a same material; and

an oxide liner disposed between the first diffusion barrier layer and the semiconductor substrate, wherein the oxide liner further extends partially between a bottom surface of the isolation layer and the top surface of the semiconductor substrate.

17. The device of claim 16 further comprising an etch-stop layer between the dielectric layer and the isolation layer, wherein the first portion of the conductive feature extends through the etch-stop layer.

18. The device of claim 16, wherein an average thickness of the first diffusion barrier layer is within 5% of an average thickness of the second diffusion barrier layer.

19. The device of claim 16 further comprising:

an additional isolation layer contacting a bottom surface of the semiconductor substrate;

an additional dielectric layer under the additional isolation layer; and

a metal pad in the additional dielectric layer, wherein the metal pad is electrically connected to the conductive feature.