System in package fan out stacking architecture and process flow

• US 9,633,974 B2
• Filed: 03/04/2015
• Issued: 04/25/2017
• Est. Priority Date: 03/04/2015
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Zhai, Jun, Hu, Kunzhong, Lai, Kwan-Yu, Pang, Mengzhi, Zhong, Chonghua, Yang, Se Young
• Primary Examiner(s): Pham, Long
• Application Number:
  US14/638,925
• Publication Number:
  US 20160260684A1
• Time in Patent Office: 783 Days
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/08167 the bonding area connecting to a bonding area disposed in a recess of the surface of the item
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/27 Manufacturing methods
• CPC Class Codes: H01L 2224/27318 by dispensing droplets
• CPC Class Codes: H01L 2224/2732 Screen printing, i.e. using a stencil
• CPC Class Codes: H01L 2224/27436 Lamination of a preform, e.g. foil, sheet or layer
• CPC Class Codes: H01L 2224/2919 with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/81193 wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83191 wherein the layer connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/83855 Hardening the adhesive by curing, i.e. thermosetting
• CPC Class Codes: H01L 2224/83862 Heat curing
• CPC Class Codes: H01L 2224/83874 Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/94 at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/0652 : Bump or bump-like direct electrical connections from substrate to substrate
• CPC Class Codes: H01L 2225/06524 : Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06572 : Auxiliary carrier between devices, the carrier having an electrical connection structure
• CPC Class Codes: H01L 23/3135 : Double encapsulation or coating and encapsulation
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5383 : Multilayer substrates H01L23/5385 takes precedence; multilayer metallisation on monolayer substrates H01L23/538
• CPC Class Codes: H01L 23/5384 : Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors H01L23/5383, H01L23/5385 take precedence; pins attached to insulating substrates H01L23/49811
• CPC Class Codes: H01L 23/5389 : the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1433 : Application-specific integrated circuit [ASIC]
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/18161 : of a flip chip
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19042 : being an inductor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate

Abstract

Packages and methods of formation are described. In an embodiment, a system in package (SiP) includes first and second redistribution layers (RDLs), and a plurality of die attached to the front and back side of the first RDL. The first and second RDLs are coupled together with a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL.

Claims

1. A package comprising:

a first die including a bottom surface that includes a first contact pad and a passivation layer;

a first redistribution layer (RDL);

wherein the first die is attached to a front side of the first RDL such that the front side of the first RDL is directly on the first contact pad and the passivation layer;

a first molding compound encapsulating the first die on the front side of the first RDL;

a top surface of a second die attached to a back side of the first RDL with a die attach film such that the second die is facing back to the first RDL;

a second RDL;

a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL;

a second molding compound encapsulating the second die and the plurality of conductive pillars between the back side of the first RDL and the front side of the second RDL.

2. The package of claim 1, further comprising a plurality of conductive bumps on a back side of the second RDL.

3. The package of claim 1, wherein the first molding compound does not completely cover a top surface of the first die.

4. The package of claim 3, wherein the second molding compound does not completely cover a bottom surface of the second die adjacent the second RDL.

5. The package of claim 1, wherein the second RDL comprises a second redistribution line formed directly on one of the plurality of conductive pillars.

6. The package of claim 5, wherein the die attach film is a cured film.

7. The package of claim 5, wherein the second RDL comprises a third redistribution line formed directly on a conductive contact of the second die.

8. The package of claim 5, wherein a bottom surface of a conductive contact of the second die, and bottom surfaces of the plurality of conductive pillars are coplanar.

9. A package comprising:

a first element including a bottom surface that includes a first contact pad and a passivation layer;

a first redistribution layer (RDL);

wherein the first element is attached to a front side of the first RDL such that the front side of the first RDL is directly on the first contact pad and the passivation layer;

a first molding compound encapsulating the first element on the front side of the first RDL;

a top surface of a second die attached to a back side of the first RDL with a die attach film such that the second die is facing back to the first RDL;

a second RDL;

a plurality of conductive pillars extending from the back side of the first RDL to a front side of the second RDL;

a second molding compound encapsulating the second die and the plurality of conductive pillars between the back side of the first RDL and the front side of the second RDL.

10. The package of claim 9, wherein the second die is a logic die.

11. The package of claim 10, wherein the first element is a memory die.

12. The package of claim 9, wherein the first RDL is less than 50 μ

m thick.

13. The package of claim 9, wherein the second RDL is less than 50 μ

m thick.

14. The package of claim 9, wherein the second RDL comprises a second redistribution line formed directly on one of the plurality of conductive pillars.

15. The package of claim 9, wherein the second RDL comprises redistribution lines formed directly on one of the plurality of conductive pillars, and directly on a conductive contact of the second die.

16. The package of claim 15, wherein the die attach film is a cured film.