Semiconductor device, solid-state image sensor and camera system

• US 9,634,052 B2
• Filed: 09/22/2016
• Issued: 04/25/2017
• Est. Priority Date: 01/08/2010
• Status: Active Grant

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Sukegawa, Shunichi, Fukushima, Noriyuki
• Primary Examiner(s): PRABHAKHER, PRITHAM DAVID
• Application Number:
  US15/273,565
• Publication Number:
  US 20170012075A1
• Time in Patent Office: 215 Days
• Field of Search: 348308
• CPC Class Codes: H01L 25/167 comprising optoelectronic devices, e.g. LED, photodiodes
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14621 Colour filter arrangements
• CPC Class Codes: H01L 27/14627 Microlenses
• CPC Class Codes: H01L 27/14634 Assemblies, i.e. Hybrid structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14643 Photodiode arrays; MOS imagers
• CPC Class Codes: H01L 27/14645 Colour imagers
• CPC Class Codes: H01L 27/1469 Assemblies, i.e. hybrid integration
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H04N 25/70 SSIS architectures; Circuits associated therewith
• CPC Class Codes: H04N 25/77 Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
• CPC Class Codes: H04N 25/772 comprising A/D, V/T, V/F, I/T or I/F converters
• CPC Class Codes: H04N 25/78 Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
• CPC Class Codes: H04N 25/79 Arrangements of circuitry being divided between different or multiple substrates, chips or circuit boards, e.g. stacked image sensors

Abstract

The present invention relates to a semiconductor device, a solid-state image sensor and a camera system capable of reducing the influence of noise at a connection between chips without a special circuit for communication and reducing the cost as a result. The semiconductor device includes: a first chip; and a second chip, wherein the first chip and the second chip are bonded to have a stacked structure, the first chip has a high-voltage transistor circuit mounted thereon, the second chip has mounted thereon a low-voltage transistor circuit having lower breakdown voltage than the high-voltage transistor circuit, and wiring between the first chip and the second chip is connected through a via formed in the first chip.

Claims

1. An imaging device comprising:

a first semiconductor substrate including;

a pixel array unit including a plurality of pixels,

a plurality of signal lines, and

a plurality of comparators, wherein at least one comparator of the plurality of comparators is coupled to at least one pixel of the plurality of pixels through at least one signal line of the plurality of signal lines; and

a second semiconductor substrate laminated with the first semiconductor substrate, the second semiconductor substrate including;

a control circuit coupled to at least one pixel of the plurality of pixels through at least one via of a first plurality of vias disposed along a first side of the pixel array unit, and

a plurality of counters, wherein at least one counter of the plurality of counters is coupled to at least one comparator of the plurality of comparators through at least one via of a second plurality of vias disposed along a second side of the pixel array unit.

2. The imaging device according to claim 1, wherein the control circuit is configured to output at least one control signal.

3. The imaging device according to claim 2, wherein at least one pixel of the plurality of pixels is configured to receive a signal based on the at least one control signal through at least one via of the first plurality of vias.

4. The imaging device according to claim 1, wherein the second plurality of vias is disposed adjacent to the plurality of comparators.

5. The imaging device according to claim 1, further comprising a plurality of pads disposed at an outermost peripheral portion of the imaging device.

6. The imaging device according to claim 1, wherein the first side of the pixel array unit is perpendicular to the second side of the pixel array unit.

7. The imaging device according to claim 1, wherein the first and second plurality of vias are disposed outside of the pixel array unit.

8. The imaging device according to claim 1, wherein the second semiconductor substrate includes a reference signal generation circuit that supplies a reference signal to the plurality of comparators.

9. The imaging device according to claim 1, wherein at least one counter of the plurality of counters is configured to receive a signal based on an output of the at least one comparator through at least one via of the second plurality of vias.

10. An imaging device comprising:

a first semiconductor substrate including;

a pixel array unit including a plurality of pixels,

a plurality of signal lines, and

a plurality of comparators, wherein at least one comparator of the plurality of comparators is coupled to at least one pixel of the plurality of pixels through at least one signal line of the plurality of signal lines;

a second semiconductor substrate laminated with the first semiconductor substrate, the second semiconductor substrate including;

a plurality of counters, and

a control circuit;

a first plurality of vias disposed along a first side of the pixel array unit; and

a second plurality of vias disposed along a second side of the pixel array unit, wherein at least one counter of the plurality of counters is coupled to at least one comparator of the plurality of comparators through at least one via of the second plurality of vias.

11. The imaging device according to claim 10, wherein the second plurality of vias is disposed adjacent to the plurality of comparators.

12. The imaging device according to claim 10, further comprising a plurality of pads disposed at an outermost peripheral portion of the imaging device.

13. The imaging device according to claim 10, wherein the first side of the pixel array unit is perpendicular to the second side of the pixel array unit.

14. The imaging device according to claim 10, wherein the first and second plurality of vias are disposed outside of the pixel array unit.

15. The imaging device according to claim 10, wherein the second semiconductor substrate includes a reference signal generation circuit that supplies a reference signal to the plurality of comparators.

16. The imaging device according to claim 10, wherein at least one counter of the plurality of counters is configured to receive a signal based on an output of the at least one comparator through at least one via of the second plurality of vias.

17. An imaging device comprising:

a first semiconductor substrate including;

a pixel array unit including a plurality of pixels,

a plurality of signal lines, and

a plurality of comparators, wherein at least one comparator of the plurality of comparators is coupled to at least one pixel of the plurality of pixels through at least one signal line of the plurality of signal lines;

a second semiconductor substrate laminated with the first semiconductor substrate, the second semiconductor substrate including a plurality of counters; and

a first plurality of vias disposed along a first side of the pixel array unit and outside of the pixel array unit, wherein at least one counter of the plurality of counters is coupled to at least one comparator of the plurality of comparators through at least one via of a first plurality of vias.

18. The imaging device according to claim 17, wherein the first plurality of vias is disposed adjacent to the plurality of comparators.

19. The imaging device according to claim 17, further comprising a plurality of pads disposed at an outermost peripheral portion of the imaging device.

20. The imaging device according to claim 17, further comprising a second plurality of vias disposed along a second side of the pixel array unit.

21. The imaging device according to claim 20, wherein the first side of the pixel array unit is perpendicular to the second side of the pixel array unit.

22. The imaging device according to claim 17, wherein the second semiconductor substrate includes a reference signal generation circuit that supplies a reference signal to the plurality of comparators.

23. The imaging device according to claim 20, further comprising at least one control circuit coupled to at least one pixel of the plurality of pixels through at least one via of the second plurality of vias.

24. The imaging device according to claim 20, wherein the second semiconductor substrate includes a control circuit configured to output a control signal.

25. An imaging device comprising:

a first semiconductor substrate including;

a pixel array unit including a plurality of pixels, and

a plurality of signal lines,

a second semiconductor substrate laminated with the first semiconductor substrate, the second semiconductor substrate including a portion of an analog-to-digital (A/D) converter; and

a first plurality of vias disposed along a first side of the pixel array unit and outside of the pixel array unit; and

a second plurality of vias disposed along a second side of the pixel array unit and outside of the pixel array unit, wherein the first side of the pixel array unit is perpendicular to the second side of the pixel array unit, and the first semiconductor substrate is electrically connected to the second semiconductor substrate via at least one via of the first plurality of vias.

26. The imaging device according to claim 25, wherein a portion of the A/D converter includes a counter.

27. The imaging device according to claim 25, wherein a plurality of pads is disposed outside of the first plurality of vias and a second plurality of vias.

28. The imaging device according to claim 25, wherein the second semiconductor substrate includes a reference signal generation circuit that supplies a reference signal.

29. The imaging device according to claim 25, wherein the first semiconductor substrate includes a comparator.

30. The imaging device according to claim 25, wherein the second semiconductor substrate includes a control circuit.