Interlayer dielectric for non-planar transistors
First Claim
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1. A method comprising:
- forming a sacrificial non-planar transistor gate over a non-planar transistor fin;
depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin;
forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate;
forming a source/drain region;
removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin;
forming a gate dielectric adjacent the non-planar transistor fin within the gate trench;
depositing conductive gate material within the gate trench;
removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers;
forming a capping dielectric structure within the recess;
forming a first interlayer dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and
forming a densified portion of the first interlayer dielectric material, which results in the densified portion of the first interlayer dielectric material and a non-densified portion of the first interlayer dielectric material layer.
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Abstract
The present description relates the formation of a first level interlayer dielectric material layer within a non-planar transistor, which may be formed by a spin-on coating technique followed by oxidation and annealing. The first level interlayer dielectric material layer may be substantially void free and may exert a tensile strain on the source/drain regions of the non-planar transistor.
61 Citations
10 Claims
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1. A method comprising:
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forming a sacrificial non-planar transistor gate over a non-planar transistor fin; depositing a dielectric material layer over the sacrificial non-planar transistor gate and the non-planar transistor fin; forming non-planar transistor gate spacers from a portion of the dielectric material layer adjacent the sacrificial non-planar transistor gate; forming a source/drain region; removing the sacrificial non-planar transistor gate to form a gate trench between the non-planar transistor gate spacers and expose a portion of the non-planar transistor fin; forming a gate dielectric adjacent the non-planar transistor fin within the gate trench; depositing conductive gate material within the gate trench; removing a portion of the conductive gate material to form a recess between the non-planar transistor gate spacers; forming a capping dielectric structure within the recess; forming a first interlayer dielectric material layer over the source/drain region, the non-planar transistor gate spacers, and the capping dielectric structure; and forming a densified portion of the first interlayer dielectric material, which results in the densified portion of the first interlayer dielectric material and a non-densified portion of the first interlayer dielectric material layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification