Patterned substrate design for layer growth

• US 9,634,189 B2
• Filed: 04/26/2016
• Issued: 04/25/2017
• Est. Priority Date: 09/06/2011
• Status: Active Grant

• Current Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Original Assignee: Sensor Electronic Technology Incorporated (Seoul Semiconductor Co., Ltd.)
• Inventors: Shatalov, Maxim S., Jain, Rakesh, Yang, Jinwei, Shur, Michael, Gaska, Remigijus
• Primary Examiner(s): Lee, Kyoung
• Assistant Examiner(s): Mehta, Ratisha
• Application Number:
  US15/138,415
• Publication Number:
  US 20160240739A1
• Time in Patent Office: 364 Days
• Field of Search: 257 98, 257730, 257 88, 257 89, 257 99, 257 94, 257 95, 257E21121, 257E21126, 257E21127, 438 29
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 21/0237 Materials
• CPC Class Codes: H01L 21/0242 Crystalline insulating materials
• CPC Class Codes: H01L 21/0243 Surface structure
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 21/02617 Deposition types
• CPC Class Codes: H01L 21/02639 Preparation of substrate for selective deposition
• CPC Class Codes: H01L 21/0265 Pendeoepitaxy
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 33/007 comprising nitride compounds
• CPC Class Codes: H01L 33/0075 comprising nitride compounds
• CPC Class Codes: H01L 33/06 within the light emitting region, e.g. quantum confinement structure or tunnel barrier
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/32 containing nitrogen

Abstract

A patterned surface for improving the growth of semiconductor layers, such as group III nitride-based semiconductor layers, is provided. The patterned surface can include a set of substantially flat top surfaces and a plurality of openings. Each substantially flat top surface can have a root mean square roughness less than approximately 0.5 nanometers, and the openings can have a characteristic size between approximately 0.1 micron and five microns. One or more of the substantially flat top surfaces can be patterned based on target radiation.

Claims

1. A device comprising:

a substrate comprising a patterned surface having a set of attributes conducive for growth of a buffer layer thereon, wherein the patterned surface includes a set of substantially flat top surfaces and a plurality of openings, wherein each substantially flat top surface includes a set of regions having a root mean square roughness less than approximately 0.5 nanometers, and wherein the plurality of openings have a characteristic size between approximately 0.1 micron and five microns;

a group III-nitride buffer layer located directly on the substrate; and

a group III-nitride light emitting active region located on the buffer layer.

2. The device of claim 1, wherein the patterned surface is formed from a plurality of protruding regions, each protruding region having one of the set of substantially flat top surfaces, wherein an opening between two adjacent protruding regions has a diameter less than or equal to a diameter of each of the top surfaces of the two adjacent protruding regions.

3. The device of claim 1, wherein the substrate is formed of one of:

sapphire, silicon, germanium, silicon carbide, a group III-nitride, or lithium gallate.

4. The device of claim 1, further comprising a group III-nitride n-type layer located between the buffer layer and the active region.

5. The device of claim 1, wherein the substrate further comprises a plurality of silicon dioxide stripes.

6. The device of claim 1, wherein each substantially flat top surface includes a set of grooves defining a plurality of regions.

7. The device of claim 1, wherein each substantially flat top surface is patterned to form a photonic crystal.

8. The device of claim 1, wherein the device is configured to operate as one of:

a light emitting diode, a laser diode, or a super-luminescent light emitting diode.

9. A method comprising:

creating a design for a patterned surface for a substrate of a device based on growth attributes for a buffer layer to be grown on the patterned surface, wherein the patterned surface includes a set of substantially flat top surfaces and a plurality of openings, wherein each substantially flat top surface includes a set of regions having a root mean square roughness less than approximately 0.5 nanometers, and wherein the plurality of openings have a characteristic size between approximately 0.1 micron and five microns; and

fabricating the device using the design, wherein the fabricating includes;

growing the buffer layer directly on the substrate; and

growing a light emitting active region on the buffer layer.

10. The method of claim 9, wherein the fabricating further includes fabricating the patterned surface prior to growing the buffer layer.

11. The method of claim 9, wherein the creating is further based on radiation propagating through an interface between the buffer layer and the substrate.

12. The method of claim 11, wherein the creating includes defining a pattern to be formed on at least some of the substantially top surfaces.

13. The method of claim 9, wherein the buffer layer is a group III-nitride layer.

14. The method of claim 13, wherein the growing uses an epitaxial process favoring lateral growth of the layer.

15. The method of claim 13, wherein the epitaxial process includes a material deposition process selected from the group consisting of:

metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or a modified version of any of MOCVD, MBE, or HVPE.

16. The method of claim 13, wherein the growing is performed at a temperature between approximately 400 degrees Celsius and approximately 1500 degrees Celsius.

17. The method of claim 13, wherein the growing is performed at a pressure between approximately 1×

10<sup>−

5</sup> Torr and approximately 1000 Torr.

18. The method of claim 13, wherein the growing uses a flux ratio between nitrogen and the group III elements in the growth chamber between approximately 1 and approximately 10000.

19. A system comprising:

a computer system configured to implement a method of fabricating a device, the method comprising;

fabricating a patterned surface for a substrate of the device based on growth attributes for a buffer layer to be grown on the patterned surface, wherein the patterned surface includes a set of substantially flat top surfaces and a plurality of openings, wherein each substantially flat top surface includes a set of regions having a root mean square roughness less than approximately 0.5 nanometers, and wherein the plurality of openings have a characteristic size between approximately 0.1 micron and five microns;

growing a group III-nitride buffer layer directly on the patterned surface of the substrate; and

growing a group III-nitride light emitting active region on the buffer layer.

20. The system of claim 19, wherein the growing uses an epitaxial process favoring lateral growth of the layer.