Wire bond free wafer level LED

• US 9,634,191 B2
• Filed: 11/14/2007
• Issued: 04/25/2017
• Est. Priority Date: 11/14/2007
• Status: Active Grant

• Current Assignee: Creeled Incorporated
• Original Assignee: CREE Incorporated (Wolfspeed, Inc.)
• Inventors: Medendorp, Jr., Nicholas W., Keller, Bernd, Chitnis, Ashay, Ibbetson, James, Batres, Max
• Primary Examiner(s): Nguyen, Thinh T
• Application Number:
  US11/985,410
• Publication Number:
  US 20090121241A1
• Time in Patent Office: 3,450 Days
• Field of Search: 257 96, 257 97, 257 98, 257 99, 257E21499, 257E21502, 257E33068, 438 22, 438 25, 438 26, 438 27, 438 29
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49107 on the semiconductor or solid-state body
• CPC Class Codes: H01L 25/0756 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/207 Diameter ranges
• CPC Class Codes: H01L 33/08 with a plurality of light emitting regions, e.g. laterally discontinuous light emitting layer or photoluminescent region integrated within the semiconductor body H01L27/15 takes precedence
• CPC Class Codes: H01L 33/22 Roughened surfaces, e.g. at the interface between epitaxial layers
• CPC Class Codes: H01L 33/385 the electrode extending at least partially onto a side surface of the semiconductor body
• CPC Class Codes: H01L 33/46 Reflective coating, e.g. dielectric Bragg reflector
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/50 Wavelength conversion elements
• CPC Class Codes: H01L 33/505 characterised by the shape, e.g. plate or foil
• CPC Class Codes: H01L 33/58 Optical field-shaping elements
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

A wire-bond free semiconductor device with two electrodes both of which are accessible from the bottom side of the device. The device is fabricated with two electrodes that are electrically connected to the oppositely doped epitaxial layers, each of these electrodes having leads with bottom-side access points. This structure allows the device to be biased with an external voltage/current source, obviating the need for wire-bonds or other such connection mechanisms that must be formed at the packaging level. Thus, features that are traditionally added to the device at the packaging level (e.g., phosphor layers or encapsulants) may be included in the wafer level fabrication process. Additionally, the bottom-side electrodes are thick enough to provide primary structural support to the device, eliminating the need to leave the growth substrate as part of the finished device.

Claims

1. A semiconductor device comprising:

an n-type epitaxial semiconductor layer comprising a first surface and a second surface opposite the first surface;

a p-type epitaxial semiconductor layer comprising a third surface and a fourth surface opposite the third surface;

an active region between the second surface and the fourth surface;

a wavelength conversion layer adjacent to at least a portion of the first surface of said n-type semiconductor layer, wherein the first surface is opposite the third surface of the p-type semiconductor layer;

a p-electrode comprising a lead that is accessible on the third surface, the third surface being opposite of a primary emission surface of said semiconductor device, said p-electrode electrically connected to said p-type layer;

an n-electrode comprising a lead that is accessible on the second surface, the second surface being opposite of said primary emission surface, said n-electrode electrically connected to said n-type layer; and

at least one spacer element, coupled to the n-electrode and the p-electrode, such that the at least one spacer element electrically isolates the n-electrode from the p-electrode, in which the n-electrode and the p-electrode extend laterally over the at least one spacer element,

wherein said first surface of said n-type epitaxial semiconductor layer is modified to enhance emission from said semiconductor device.

2. The semiconductor device of claim 1, further comprising:

an n-pad contacting said n-type layer and providing an electrical connection between said n-type layer and said n-electrode; and

a p-pad contacting said p-type layer and providing an electrical connection between said p-type layer and said p-electrode.

3. The semiconductor device of claim 2, wherein said n-pad partially overlaps said p-pad, said n- and p-pads electrically isolated by a spacer element.

4. The semiconductor device of claim 2, wherein said p-pad partially overlaps said n-pad, said p- and n-pads electrically isolated by a spacer element.

5. The semiconductor device of claim 2, wherein said p-pad comprises a reflective material.

6. The semiconductor device of claim 1, said wavelength conversion layer comprising a phosphor layer opposite said leads of said n- and p-electrodes such that said phosphor layer comprises said primary emitting surface.

7. The semiconductor device of claim 6, wherein said phosphor layer is disposed on said p-type layer.

8. The semiconductor device of claim 7, further comprising a current spreading layer interposed between said phosphor layer and said p-type layer, said current spreading layer electrically connected to said p-electrode.

9. The semiconductor device of claim 1, in which the at least one spacer element electrically isolates both said n- and p-electrodes from said active region.

10. The semiconductor device of claim 9, wherein said at least one spacer element comprises a dielectric material.

11. The semiconductor device of claim 9, wherein said at least one spacer element comprises a polymer.

12. The semiconductor device of claim 1, wherein substantially all of said n-type layer, said active region and said p-type layer are above said p-electrode.

13. The semiconductor device of claim 1, wherein said n-type layer, said p-type layer and said active region comprise materials from the Group-III Nitrides.

14. The semiconductor device of claim 1, wherein the thickness of said p-electrode is at least 20 μ

m and the thickness of said n-electrode is at least 20 μ

m.

15. The semiconductor device of claim 1, wherein the thickness of said p-electrode is at least 50 μ

m and the thickness of said n-electrode is at least 50 μ

m.

16. The semiconductor device of claim 1, wherein substantially all of said n-type layer, said active region and said p-type layer are disposed between said n-electrode and said primary emission surface.

17. The semiconductor device of claim 1, wherein said wavelength conversion layer is adjacent to said n-type semiconductor layer.

18. A semiconductor chip device, comprising:

an n-type semiconductor layer comprising a primary emission surface;

a p-type semiconductor layer;

an active region between said n- and p-type layers;

an n-electrode integral to said semiconductor chip device and comprising a lead that is accessible on a surface opposite said primary emission surface, said n-electrode electrically coupled to said n-type semiconductor layer;

a p-electrode integral to said semiconductor chip device and comprising a lead that is accessible on a surface opposite said primary emission surface, said p-electrode electrically coupled to said p-type semiconductor layer;

at least one spacer element, coupled to the n-electrode and the p-electrode, such that the at least one spacer element electrically isolates the n-electrode from the p-electrode and further electrically isolates the n-pad and the p-pad from the active region, in which the n-electrode and the p-electrode extend laterally over the at least one spacer element; and

a phosphor layer coupled to the primary emission surface, wherein said primary emission surface of said n-type semiconductor layer is modified.

19. The semiconductor device of claim 18, further comprising:

an n-pad contacting said n-type layer and providing an electrical connection between said n-type layer and said n-electrode; and

a p-pad contacting said p-type layer and providing an electrical connection between said p-type layer and said p-electrode.

20. The semiconductor device of claim 19, wherein said p-pad comprises a reflective material.

21. The semiconductor device of claim 18, wherein the phosphor layer is coupled to the wafer opposite said leads of said n- and p-electrodes.

22. The semiconductor device of claim 18, further comprising at least one spacer element configured to electrically isolate said n-electrode from said p-electrode and to electrically isolate both said n- and p-electrodes from said active region.

23. The semiconductor device of claim 18, wherein substantially all of said n-type layer, said active region and said p-type layer are above said p-electrode.

24. The semiconductor device of claim 18, wherein said n-type layer, said p-type layer and said active region comprise materials from the Group-III Nitrides.

25. The semiconductor device of claim 18, wherein the thickness of said p-electrode is at least 50 μ

m and said n-electrode is at least 50 μ

m.

26. A semiconductor Group-III nitride device, comprising:

a flip-chip light emitting diode (LED) structure comprising an active region between a first surface of an n-type layer and a p-type layer;

an n-pad electrically coupled to the first surface of said n-type layer;

a wavelength conversion layer, coupled to at least a second surface of the n-type layer;

a p-pad electrically coupled to said p-type layer opposite an emission surface of the wavelength conversion layer, the emission surface of the wavelength conversion layer being opposite the second surface of the n-type layer;

at least one spacer element, coupled to at least the p-pad, in which the at least one spacer element electrically isolates the n-pad from the p-pad and further electrically isolates the n-pad and the p-pad from the active region; and

an electrode layer, coupled to the p-pad and the at least one spacer element, the electrode layer patterned into at least one n-electrode and at least one p-electrode, in which patterning the electrode layer defines the at least one n-electrode and the at least one p-electrode and the defined at least one n-electrode and the defined at least one p-electrode are electrically isolated by the at least one spacer element;

wherein said at least one n-electrode and said at least one p-electrode are exposed on a side of said semiconductor device opposite said n-type layer such that said semiconductor device is mountable to a surface, and

wherein the second surface of said n-type layer is modified to enhance light emission from the emission surface of the semiconductor device.

27. A semiconductor device, comprising:

a light emitter structure comprising;

an n-type layer;

an active region coupled to a first surface of the n-type region;

a p-type layer coupled to the active region opposite the n-type layer,

a wavelength conversion layer coupled to a second surface of the n-type layer, wherein the second surface of said n-type layer is opposite said active layer and is modified to enhance light emission through the second surface of the n-type layer into the wavelength conversion layer;

an n-electrode electrically coupled to said n-type layer;

a p-electrode electrically coupled to said p-type layer; and

at least one spacer element, coupled to the n-electrode and the p-electrode, such that the at least one spacer element electrically isolates the n-electrode from the p-electrode and the n-electrode and the p-electrode extend laterally over the at least one spacer element.

28. A semiconductor device, comprising:

a flip-chip light emitting diode (LED) structure comprising an active region between an n-type layer and a p-type layer;

an n-electrode electrically coupled to said n-type layer;

a p-electrode electrically coupled to said p-type layer;

at least one spacer element, coupled to the n-electrode and the p-electrode such that the n-electrode and the p-electrode extend laterally over at least a portion of the at least one spacer element;

a wavelength conversion layer on said n-type layer and said p-type layer;

wherein said n-electrode and said p-electrode are exposed on a side of said semiconductor device opposite said n-type layer such that said semiconductor device is mountable to a surface wherein said n-electrode and said p-electrode are coplanar; and

wherein said n-type layer comprises a modified surface, said modified surface coupled to said wavelength conversion layer.

29. The semiconductor device of claim 28, further comprising a substrate on said n-type layer opposite said active region.

30. The semiconductor device of claim 29, wherein said substrate is shaped or textured to enhance light extraction.