Semiconductor device

• US 9,634,674 B2
• Filed: 08/27/2015
• Issued: 04/25/2017
• Est. Priority Date: 10/10/2014
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Jong-Pil, Lee, Young-Joo
• Primary Examiner(s): TIEU, JANICE N
• Application Number:
  US14/837,731
• Publication Number:
  US 20160105188A1
• Time in Patent Office: 607 Days
• Field of Search: 375354, 375373, 375375-376, 5354, 5373, 5375-376
• CPC Class Codes: H03L 7/0805 the loop being adapted to provide an additional control signal for use outside the loop
• CPC Class Codes: H03L 7/0814 the phase shifting device being digitally controlled
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/18 using a frequency divider or counter in the loop H03L7/20, H03L7/22 take precedence
• CPC Class Codes: H03L 7/23 with pulse counters or frequency dividers
• CPC Class Codes: H04B 5/70 specially adapted for specific purposes
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines

Abstract

A semiconductor device including a PLL providing candidate clocks of different phases in response to a first clock received from a reader via an antenna, a phase difference detector detecting a phase difference between the first clock and a clock from the candidate clocks, a phase difference controller that selects another clock from the candidate clocks, and a driver that provides transmission data synchronously with the another clock to the reader.

Claims

1. A semiconductor device comprising:

a phase locked loop (PLL) that receives a reference clock and derives candidate clocks from the reference clock, wherein each one of the candidate clocks has a different phase;

a multiplexer that receives the candidate clocks and selects a first selected clock from among the candidate clocks in response to a first control value and selects a second selected clock from among the candidate clocks, different from the first selected clock, in response to a second control value;

a phase difference detector that detects a phase difference between the reference clock and the first selected clock;

a phase difference controller generates the second control value in response to the detected phase difference;

a variable delay line that generates a transmission clock in response to the second selected clock; and

a driver that provides transmission data synchronously with the transmission clock.

2. The semiconductor device of claim 1, wherein the PLL comprises a voltage controlled oscillator (VCO) that provides the candidate clocks.

3. The semiconductor device of claim 1, further comprising:

a memory that stores a predetermined phase difference, wherein the second selected clock is a clock among the candidate clocks having a phase difference relative to the reference clock that is closest to the predetermined phase difference.

4. The semiconductor device of claim 3, wherein the phase difference controller determines the second control value in response to a first time period during which the reference clock is initially received and a second time period during which the driver initially provides the transmission data.

5. The semiconductor device of claim 1, wherein the semiconductor device is configured as a near field communication (NFC) card and further comprises an antenna.

6. The semiconductor device of claim 5, further comprising:

a field level detector that detects a level of a field generated between an externally disposed reader and the antenna, wherein the phase difference controller generates the second control value in response to an output of the field level detector.

7. A near field communication (NFC) card comprising:

an antenna;

a clock generator that generates a transmission clock; and

a driver that provides transmission data to the antenna synchronously with the transmission clock,

wherein the clock generator comprises;

a phase locked loop (PLL) that derives candidate clocks from a reference clock, wherein each one of the candidate clocks has a different phase respectively defined by m divisions of the reference clock, where ‘

m’

is a natural number;

a multiplexer that receives the candidate clocks and selects a first selected clock from among the candidate clocks in response to a first control value and selects a second selected clock from among the candidate clocks in response to a second control value;

a phase difference detector that detects a phase difference between the reference clock and the first selected clock;

a phase difference controller generates the second control value in response to the detected phase difference; and

a variable delay line that generates the transmission clock in response to the second selected clock.

8. The NFC card of claim 7, wherein the clock generator further comprises a clock receiver that generates the reference clock in response to a signal received from an externally disposed reader.

9. The NFC card of claim 8, further comprising:

a field level detector that detects a level of a field generated between the externally disposed reader and the antenna, wherein the phase difference controller generates the second control value in response to an output of the field level detector.