Clock generator and integrated circuit using the same and injection-locked phase-locked loop control method

• US 9,634,677 B2
• Filed: 02/24/2016
• Issued: 04/25/2017
• Est. Priority Date: 07/23/2015
• Status: Active Grant

• Current Assignee: MediaTek, Inc.
• Original Assignee: MediaTek, Inc.
• Inventors: Huang, Yi-Chieh
• Primary Examiner(s): HOUSTON, ADAM D
• Application Number:
  US15/052,183
• Publication Number:
  US 20170026048A1
• Time in Patent Office: 426 Days
• Field of Search: 327147-149, 327156-158
• CPC Class Codes: H03L 7/22 using more than one loop
• CPC Class Codes: H03L 7/24 using a reference signal directly applied to the generator

Abstract

A control technique for an injection-locked phase-locked loop (ILPLL) includes the following steps: providing the ILPLL with a sampling clock and an injection clock for an integral path and a proportional path of the ILPLL, respectively; making a change in the power level of the injection clock to get the phase error of the integral path of the ILPLL; and controlling the phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the ILPLL.

Claims

1. A clock generator, comprising:

an injection-locked phase-locked loop for generation of an output clock, receiving a sampling clock and an injection clock for an integral path and a proportional path of the injection-locked phase-locked loop, respectively;

a pulse-power controller, controlling power level of the injection clock;

delay elements for the sampling clock and the injection clock; and

a delay control circuit, coupled between the injection-locked phase-locked loop and the delay elements to control the delay elements based on a phase error of the integral path of the injection-locked phase-locked loop, wherein the phase error is due to a change, caused by the pulse-power controller, in the power level of the injection clock.

2. The clock generator as claimed in claim 1, wherein:

the delay control circuit controls the delay elements to adjust a phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the injection-locked phase-locked loop to reduce reference spur of the output clock.

3. The clock generator as claimed in claim 2, wherein:

the pulse-power controller makes the change in the power level of the injection clock every N cycles of the injection clock; and

N is an integer number.

4. The clock generator as claimed in claim 3, wherein:

during the other cycles of the injection clock without the change in the power level of the injection clock, the delay control circuit controlling the delay elements makes no change on the phase difference between the sampling clock and the injection clock.

5. The clock generator as claimed in claim 2, wherein:

the pulse-power controller deviates the power level of the injection clock from a desired level to cause the change in the power level of the injection clock and thereby the phase error of the integral path of the injection-locked phase-locked loop is observable.

6. The clock generator as claimed in claim 5, wherein:

the pulse-power controller reduces the power level of the injection clock to cause the change in the power level of the injection clock.

7. The clock generator as claimed in claim 2, wherein:

the delay elements are digitally-controlled delay lines.

8. The clock generator as claimed in claim 2, wherein the injection-locked phase-locked loop comprises:

an injection-locked voltage-controlled oscillator receiving the injection clock for injection locking of the output clock; and

a flip-flop, having a D terminal receiving a first oscillation signal from the injection-locked voltage-controlled oscillator, a DB terminal receiving a second oscillation signal from the injection-locked voltage-controlled oscillator, a clock terminal receiving the sampling clock and a Q terminal outputting the phase error of the integral path of the injection-locked phase-locked loop.

9. The clock generator as claimed in claim 8, wherein:

the first oscillation signal and the second oscillation signal are transformed to the output clock.

10. The clock generator as claimed in claim 9, wherein:

the flip-flop is a sense amplifier D flip-flop.

11. The clock generator as claimed in claim 2, wherein the injection-locked phase-locked loop comprises:

an injection-locked voltage-controlled oscillator receiving the injection clock for injection locking of the output clock; and

a flip-flop, sampling an oscillation signal from the injection-locked voltage-controlled oscillator according to the sampling clock to provide the delay control circuit with the phase error of the integral path of the injection-locked phase-locked loop.

12. A control method for an injection-locked phase-locked loop for generation of an output clock, comprising:

providing the injection-locked phase-locked loop with a sampling clock and an injection clock for an integral path and a proportional path of the injection-locked phase-locked loop, respectively; and

controlling a phase difference between the sampling clock and the injection clock based on the phase error of the integral path of the injection-locked phase-locked loop by making a change in the power level of the injection clock to get a phase error of the integral path of the injection-locked phase-locked loop.

13. The control method as claimed in claim 12, wherein:

the phase difference between the sampling clock and the injection clock is adjusted to reduce reference spur of the output clock.

14. The control method as claimed in claim 13, further comprising:

making the change in the power level of the injection clock every N cycles of the injection clock, where N is an integer number.

15. The control method as claimed in claim 14, wherein:

during the other cycles of the injection clock without the change in the power level of the injection clock, no change is made on the phase difference between the sampling clock and the injection clock.

16. The control method as claimed in claim 13, wherein:

the change in the power level of the injection clock is caused from deviating power level of the injection clock from the desired level and thereby the phase error of the integral path of the injection-locked phase-locked loop is observable.

17. The control method as claimed in claim 16, wherein:

the change in the power level of the injection clock is caused from reducing the power level of the injection clock.

18. The control method as claimed in claim 13, furthering comprising:

providing an injection-locked voltage-controlled oscillator and a flip-flop within the injection-locked phase-locked loop,

wherein;

the injection-locked voltage-controlled oscillator receives the injection clock for injection locking of the output clock; and

the flip-flop has a D terminal receiving a first oscillation signal from the injection-locked voltage-controlled oscillator, a DB terminal receiving a second oscillation signal from the injection-locked voltage-controlled oscillator, a clock terminal receiving the sampling clock, and a Q terminal outputting the phase error of the integral path of the injection-locked phase-locked loop.

19. The control method as claimed in claim 13, furthering comprising:

providing an injection-locked voltage-controlled oscillator and a flip-flop within the injection-locked phase-locked loop,

wherein;

the injection-locked voltage-controlled oscillator receives the injection clock for injection locking of the output clock; and

the flip-flop samples an oscillation signal from the injection-locked voltage-controlled oscillator according to the sampling clock to output a signal indicating the phase error of the integral path of the injection-locked phase-locked loop.