Semiconductor apparatus
First Claim
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1. A semiconductor apparatus comprising:
- a test entry control block configured to enable a plurality of trigger signals in a predetermined order in response to a test setting command and addresses successively inputted, and enable a reset signal when another command other than the test setting command is inputted; and
a test entry signal generation block configured to sequentially enable a plurality of pre-test entry signals when the plurality of trigger signals are enabled in the predetermined order, and enable a test entry signal when a final pre-test entry signal among the plurality of pre-test entry signals is enabled,wherein the final pre-test entry signal is enabled when all the plurality of pre-test entry signals are enabled.
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Abstract
A semiconductor apparatus includes a test entry control block configured to generate a plurality of trigger signals and a reset signal according to a test setting command and addresses; and a test entry signal generation block configured to enable a test entry signal when the plurality of trigger signals are sequentially enabled.
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Citations
10 Claims
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1. A semiconductor apparatus comprising:
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a test entry control block configured to enable a plurality of trigger signals in a predetermined order in response to a test setting command and addresses successively inputted, and enable a reset signal when another command other than the test setting command is inputted; and a test entry signal generation block configured to sequentially enable a plurality of pre-test entry signals when the plurality of trigger signals are enabled in the predetermined order, and enable a test entry signal when a final pre-test entry signal among the plurality of pre-test entry signals is enabled, wherein the final pre-test entry signal is enabled when all the plurality of pre-test entry signals are enabled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification