Data clock synchronization in hybrid memory modules
First Claim
1. A hybrid memory module comprising:
- a package to contain multiple memory module components;
a first set of the memory module components comprising one or more flash memory devices;
a second set of the memory module components comprising one or more DRAM devices;
a non-volatile memory controller coupled to at least one of the DRAM devices to communicate one or more data signals to at least one of the flash memory devices;
at least one command buffer electrically coupled to the non-volatile memory controller and electrically coupled to the DRAM devices, the at least one command buffer to receive a local clock signal from the non-volatile memory controller, and to provide at least one synchronized data clock signal to the DRAM devices; and
a clock synchronization engine to generate the synchronized data clock signal based at least in part on the local clock signal, wherein a first phase relationship between the synchronized data clock signal and the data signals facilitate latching of the data signals at the DRAM devices, and wherein the first phase relationship compensates for at least one of, one or more synchronous delays, one or more asynchronous delays, or a combination of at least one of the one or more synchronous delays and at least one of the one or more asynchronous delays.
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Accused Products
Abstract
Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller. In other embodiments, certain fixed and/or programmable delay elements can be implemented to compensate for various asynchronous delays.
10 Citations
20 Claims
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1. A hybrid memory module comprising:
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a package to contain multiple memory module components; a first set of the memory module components comprising one or more flash memory devices; a second set of the memory module components comprising one or more DRAM devices; a non-volatile memory controller coupled to at least one of the DRAM devices to communicate one or more data signals to at least one of the flash memory devices; at least one command buffer electrically coupled to the non-volatile memory controller and electrically coupled to the DRAM devices, the at least one command buffer to receive a local clock signal from the non-volatile memory controller, and to provide at least one synchronized data clock signal to the DRAM devices; and a clock synchronization engine to generate the synchronized data clock signal based at least in part on the local clock signal, wherein a first phase relationship between the synchronized data clock signal and the data signals facilitate latching of the data signals at the DRAM devices, and wherein the first phase relationship compensates for at least one of, one or more synchronous delays, one or more asynchronous delays, or a combination of at least one of the one or more synchronous delays and at least one of the one or more asynchronous delays. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification