Utilizing a cache mechanism by copying a data set from a cache-disabled memory location to a cache-enabled memory location

• US 9,639,473 B1
• Filed: 11/06/2015
• Issued: 05/02/2017
• Est. Priority Date: 12/09/2014
• Status: Active Grant

• Current Assignee: DataRobot, Inc.
• Original Assignee: Parallel Machines Ltd.
• Inventors: Adda, Michael, Braverman, Avner, Aloni, Dan, Khermosh, Lior, Zuckerman, Gal, Amar, Lior
• Primary Examiner(s): KIM, HONG CHONG
• Application Number:
  US14/934,252
• Time in Patent Office: 543 Days
• Field of Search: 711138, 711139, 711118
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/452 Instruction code

Abstract

Described herein are systems and methods to prevent a controller in a DDIO (data direct input output) system from shifting currently-required data out of a cache memory. In one embodiment, a compute element disables caching of some specific addresses in a non-cache memory, but still enables caching of other addresses in the non-cache memory, thereby practically disabling the DDIO system, so that data sets not currently needed are placed in the addresses in the non-cache memory which are not cached. As a result, currently-required data are not shifted out of cache memory. The compute element then determines that the data sets, which formerly avoided being cached, are now required. The system therefore copies the data sets that are now required from addresses in non-cache memory not accessible to cache memory, to addresses in non-cache memory accessible to cache memory, thereby allowing the caching and processing of such data sets.

Claims

1. A system operative to prevent a controller from automatically writing to a cache memory, comprising:

a compute element;

a memory operative to store data sets;

a cache memory associated with the compute element and operative to cache the data sets in conjunction with the memory; and

a controller operative to transfer data sets automatically from a data source to the cache memory, in which the data sets transferred are associated with specific addresses in the memory, thereby facilitating later updating of the data sets from the cache memory to the specific addresses in the memory,

wherein;

the system is configured to disable caching by the cache memory of at least the specific addresses in the memory, while still enabling caching by the cache memory of other addresses in the memory;

the controller is configured, as a result of said disablement, to refrain from said transferring of data sets automatically from the data source to the cache memory, and instead, transfer the data sets from the data source to the specific addresses in the memory; and

the compute element is configured to;

(i) determine that the data sets are now needed for processing, and should therefore be cached in the cache memory, and (ii) cause the system, as a result of said determination, to copy the data sets from the specific addresses in the memory to the other addresses in the memory, thereby now allowing the caching and processing of the data sets.

2. The system of claim 1, wherein said disablement of caching, by the cache memory, of at least the specific addresses in the memory, is achieved using a cache configuration mechanism.

3. The system of claim 2, wherein the cache configuration mechanism comprises memory-type-range-registers (MTRRs), in which the MTRRs are used to program the cache configuration mechanism so as to disable caching by the cache memory of at least the specific addresses in the memory, while still enabling caching by the cache memory of other addresses in the memory.

4. The system of claim 1, wherein the controller, operative to transfer data sets automatically from the data source to the cache memory, is of data-direct-input-output (DDIO) type.

5. The system of claim 1, wherein the data source is an input-output interface.

6. The system of claim 5, wherein the input-output interface is a network-interface-controller (NIC).

7. The system of claim 5, wherein the input-output interface is a data store.

8. The system of claim 1, wherein said copying the data sets from the specific addresses in the memory to the other addresses in the memory is performed by the compute element.

9. The system of claim 1, wherein said copying the data sets from the specific addresses in the memory to the other addresses in the memory is performed by a direct-memory-access (DMA) procedure, and is triggered by the compute element.

10. The system of claim 1, wherein:

the cache memory and the compute element are embedded in a single integrated central-processing-unit (CPU).

11. The system of claim 10, wherein the controller is also embedded in the CPU.

12. The system of claim 10, wherein the memory is located outside of the CPU.

13. The system of 12, wherein the memory is a random-access-memory (RAM).

14. The system of 12, wherein the memory is a memory module.

15. A system operative to control data sets and the caching thereof, comprising:

a compute element;

a memory configured to store a plurality of data sets; and

a cache memory associated with the compute element,

wherein;

the system is configured to allow caching, in conjunction with the cache memory, of only those of the data sets that are stored in a first part of the memory, thereby preventing caching of the other data sets that are stored in a second part of the memory;

the system is further configured to;

(i) receive, from a data source external to the system, a first data set, and (ii) direct the first data set to the second part of the memory, thereby preventing the first data set from being cached in conjunction with the cache memory; and

the compute element is configured to;

(i) determine that the first data set is now needed, and should therefore be cached in the cache memory, and (ii) cause the system, as a result of said determination, to copy the first data set from the second part of the memory to the first part of the memory, thereby allowing caching of the first data set.

16. The system of claim 15, wherein said prevention of caching is achieved using a cache configuration mechanism.

17. The system of claim 16, wherein the cache configuration mechanism comprises memory-type-range-registers (MTRRs), in which the MTRRs are used to program the cache configuration mechanism such as to disable caching by the cache memory of the second part, while still enabling caching by the cache memory of the first part.

18. A method for preventing a controller from shifting valuable data out of cache memory, comprising:

disabling, by a compute element, caching by a cache memory of at least specific addresses in a memory, while still enabling caching by the cache memory of other addresses in the memory;

affecting a controller, as a result of said disabling, such as to cause the controller to refrain from transferring of data sets automatically from a data source to the cache memory, thereby preventing the controller from shifting valuable other data sets out of the cache memory, and consequently forcing the controller to, instead, transfer the data sets from the data source to the specific addresses in the memory, in which the specific addresses in the memory are the original final destination of the data sets as determined by the data source;

determining, by the compute element, that the data sets are now needed for processing, and should therefore be cached in the cache memory; and

copying, as a result of said determination, the data sets from the specific addresses in the memory to the other addresses in the memory, thereby now allowing the caching and processing of the data sets.

19. The method of claim 18, wherein:

the valuable other data sets are data sets that are currently used by the compute element in conjunction with a processing task; and

at the time of said determination, the processing task has been concluded, the valuable other data sets are no longer needed in the cache memory, and therefore said allowing of the caching is now desirable.