Integrated circuit chip reliability using reliability-optimized failure mechanism targeting

• US 9,639,645 B2
• Filed: 06/18/2015
• Issued: 05/02/2017
• Est. Priority Date: 06/18/2015
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bickford, Jeanne P., Habib, Nazmul, Li, Baozhen, Wilder, Tad J.
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/742,801
• Publication Number:
  US 20160371413A1
• Time in Patent Office: 684 Days
• CPC Class Codes: G06F 2119/02 Reliability analysis or reliability optimisation; Failure analysis, e.g. worst case scenario performance, failure mode and effects analysis [FMEA]
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Disclosed are methods for improving integrated circuit (IC) chip reliability. IC chips are manufactured and sorted into groups corresponding to process windows within a process distribution for the design. Group fail rates are set for each group based on failure mechanism fail rates, which are set for multiple failure mechanisms. An overall fail rate is determined for the full process distribution based on the group fail rates. First contribution amounts of the groups to the overall fail rate and second contribution amounts of the failure mechanisms to the group fail rate of each group are determined. Based on an analysis of the contribution amounts, at least one specific failure mechanism is selected and targeted for improvement (i.e., changes directed to the specific failure mechanism(s) are proposed and implemented). Optionally, proposed change(s) are only implemented if they will be sufficient to meet a reliability requirement and/or will not be cost-prohibitive.

Claims

1. A method comprising:

sorting, using a computer, integrated circuit chips manufactured according to a design into groups, said groups corresponding to different process windows within a process distribution for said design;

setting group fail rates for said groups, each group fail rate for each group being based on failure mechanism fail rates set for multiple failure mechanisms;

determining an overall fail rate based on said group fail rates; and

,

improving integrated circuit chip reliability using reliability-optimized failure mechanism targeting, said improving comprising;

determining first contribution amounts of said groups to said overall fail rate;

determining, for each group fail rate of each group, second contribution amounts of said failure mechanisms to said group fail rate;

based on an analysis of said first contribution amounts and said second contribution amounts, selecting at least one specific failure mechanism; and

implementing at least one change to at least one process performed during manufacturing of new integrated circuit chips according to said design, said at least one change being directed toward improving said specific failure mechanism.

2. The method of claim 1, each first contribution amount for each group being a product of a fraction of a total number of said integrated circuit chips that were manufactured and that are in said group multiplied by a group fail rate for said group.

3. The method of claim 1, each second contribution amount for each failure mechanism in each group being an average failure mechanism fail rate for all integrated circuit chips in said group.

4. The method of claim 1, said selecting comprising:

identifying a specific group that is a highest contributor to said overall fail rate; and

identifying at least one specific failure mechanism that is a highest contributor to a specific group fail rate of said specific group.

5. The method of claim 1, further comprising, before said setting of said group fail rates, generating, for each integrated circuit chip in each group, models of said failure mechanisms as a function of a process window associated with said group.

6. The method of claim 1, further comprising performing stress testing of a sample of said new integrated circuit chips.

7. The method of claim 1, said specific failure mechanism comprising any of hot carrier injection (HCI), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), soft error rate (SER), retention disturbance, stress migration (SM) and electromigration (EM).

8. A method comprising:

sorting, using a computer, integrated circuit chips manufactured according to a design into groups, said groups corresponding to different process windows within a process distribution for said design;

setting group fail rates for said groups, each group fail rate for each group being based on failure mechanism fail rates set for multiple failure mechanisms;

determining an overall fail rate based on said group fail rates; and

,

improving integrated circuit chip reliability using reliability-optimized failure mechanism targeting, said improving comprising;

determining first contribution amounts of said groups to said overall fail rate;

determining, for each group fail rate of each group, second contribution amounts of said failure mechanisms to said group fail rate;

based on an analysis of said first contribution amounts and said second contribution amounts, selecting at least one specific failure mechanism;

proposing at least one change to at least one process performed during manufacturing of new integrated circuit chips, said at least one change being directed toward improving said specific failure mechanism;

determining expected fail rate change percentages for said failure mechanisms given said at least one change;

based on said expected fail rate change percentages, determining a predicted overall fail rate;

comparing said predicted overall fail rate to a predetermined fail rate threshold;

when said predicted overall fail rate is higher than said predetermined fail rate threshold, iteratively repeating said proposing of said at least one change, said determining of said expected fail rate change percentages, said determining of said predicted overall fail rate and said comparing until said predicted overall fail rate is lower than said predetermined fail rate threshold; and

when said predicted overall fail rate is lower than said predetermined fail rate threshold, implementing any proposed changes.

9. The method of claim 8, each first contribution amount for each group being a product of a fraction of a total number of said integrated circuit chips that were manufactured and that are in said group multiplied by a group fail rate for said group.

10. The method of claim 8, each second contribution amount for each failure mechanism in each group being an average failure mechanism fail rate for all integrated circuit chips in said group.

11. The method of claim 8, said selecting comprising:

identifying a specific group that is a highest contributor to said overall fail rate; and

identifying at least one specific failure mechanism that is a highest contributor to a specific group fail rate of said specific group.

12. The method of claim 8, further comprising, before said setting of said group fail rates, generating, for each integrated circuit chip in each group, models of said failure mechanisms as a function a process window associated with said group.

13. The method of claim 8, further comprising performing stress testing of a sample of said new integrated circuit chips.

14. The method of claim 8, said specific failure mechanism comprising any of hot carrier injection (HCI), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), soft error rate (SER), retention disturbance, stress migration (SM) and electromigration (EM).

15. A method comprising:

sorting, using a computer, integrated circuit chips manufactured according to a design into groups, said groups corresponding to different process windows within a process distribution for said design;

setting group fail rates for said groups, each group fail rate for each group being based on failure mechanism fail rates set for multiple failure mechanisms;

determining an overall fail rate based on said group fail rates; and

,

improving integrated circuit chip reliability using reliability-optimized failure mechanism targeting, said improving comprising;

determining first contribution amounts of said groups to said overall fail rate;

determining, for each group fail rate of each group, second contribution amounts of said failure mechanisms to said group fail rate;

based on an analysis of said first contribution amounts and said second contribution amounts, selecting at least one specific failure mechanism;

proposing at least one change to at least one process performed during manufacturing of new integrated circuit chips, said at least one change being directed toward improving said specific failure mechanism;

determining expected fail rate change percentages for said failure mechanisms given said at least one change;

based on said expected fail rate change percentages, determining a predicted overall fail rate;

comparing said predicted overall fail rate to a predetermined fail rate threshold;

when said predicted overall fail rate is higher than said predetermined fail rate threshold, iteratively repeating said proposing of said at least one change, said determining of said expected fail rate change percentages, said determining of said predicted overall fail rate and said comparing until said predicted overall fail rate is lower than said predetermined fail rate threshold; and

when said predicted overall fail rate is lower than said predetermined fail rate threshold and a cost of implementing any proposed changes is less than a predetermined cost threshold, implementing said proposed changes.

16. The method of claim 15, each first contribution amount for each group being a product of a fraction of a total number of said integrated circuit chips that were manufactured and that are in said group multiplied by a group fail rate for said group.

17. The method of claim 15, each second contribution amount for each failure mechanism in each group being an average failure mechanism fail rate for all integrated circuit chips in said group.

18. The method of claim 15, said selecting comprising:

identifying a specific group that is a highest contributor to said overall fail rate; and

identifying at least one specific failure mechanism that is a highest contributor to a specific group fail rate of said specific group.

19. The method of claim 15, further comprising performing stress testing of a sample of said new integrated circuit chips.

20. The method of claim 15, said specific failure mechanism comprising any of hot carrier injection (HCI), negative bias temperature instability (NBTI), positive bias temperature instability (PBTI), soft error rate (SER), retention disturbance, stress migration (SM) and electromigration (EM).