CMOS device with reading circuit

• US 9,640,228 B2
• Filed: 12/12/2014
• Issued: 05/02/2017
• Est. Priority Date: 12/12/2014
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Ioannou, Dimitris P., Kothandaraman, Chandrasekharan
• Primary Examiner(s): Rossoshek, Helen
• Application Number:
  US14/568,966
• Publication Number:
  US 20160172011A1
• Time in Patent Office: 872 Days
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G11C 11/412 using field-effect transistors only
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/24 Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/7815 with voltage or current sensing structure, e.g. emulator section, overcurrent sensing cell

Abstract

Methods and devices for providing unclonable chip identification are provided. An integrated circuit device includes: a first transistor having a first gate oxide thickness; a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor.

Claims

1. An integrated circuit device, comprising:

a first transistor having a first gate oxide thickness;

a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and

a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor, and the reading circuit comprises a first inverter and a second inverter cross-coupled between the first transistor and the second transistor.

2. The device of claim 1, wherein:

the first transistor has a first bias temperature instability (BTI)-shifted threshold voltage; and

the second transistor has a second BTI-shifted threshold voltage.

3. The device of claim 2, the first transistor and the second transistor have a same channel length and a same channel width.

4. The device of claim 1, wherein:

the first transistor is included in a first group of transistors; and

a distribution of BTI-shifted threshold voltage of the first group of transistors has a first mean and a first standard deviation;

the second transistor is included in a second group of transistors;

a distribution of BTI-shifted threshold voltage of the second group of transistors has a second mean and a second standard deviation;

the first mean equals the second mean; and

the first standard deviation is different than the second standard deviation.

5. The device of claim 1, wherein:

a drain of the first transistor is connected to an output of the first inverter and an input of the second inverter; and

a drain of the second transistor is connected to an input of the first inverter and an output of the second inverter.

6. An integrated circuit device, comprising:

an array of cells, wherein each cell comprises;

a first transistor having a first gate oxide thickness; and

a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and

a reading circuit connected to the first transistor and the second transistor of each said cell, the reading circuit comprising a first inverter and a second inverter cross-coupled between the first transistor and the second transistor,

wherein the first transistors of the cells of the array have a first threshold voltage distribution having a first mean and a first standard deviation;

the second transistors of the cells of the array have a second threshold voltage distribution having a second mean and a second standard deviation;

the first mean equals the second mean; and

the first standard deviation is different than the second standard deviation.

7. The device of claim 6, wherein:

the first threshold voltage distribution is a first post-BTI distribution that is shifted from a pre-BTI distribution of the first transistors of the cells of the array; and

the second threshold voltage distribution is a second post-BTI distribution that is shifted from a pre-BTI distribution of the second transistors of the cells of the array.

8. The device of claim 6, wherein in each of the cells:

the second gate oxide thickness is greater than the first gate oxide thickness;

a drain of the first transistor is connected to an output of the first inverter and an input of the second inverter; and

a drain of the second transistor is connected to an input of the first inverter and an output of the second inverter.

9. The device of claim 8, wherein:

the first transistors of the cells of the array and the second transistors of the cells of the array have a same channel length and a same channel width; and

the first transistors of the cells of the array and the second transistors of the cells of the array are silicon-on-insulator n-type field effect transistors.

10. The device of claim 6, the cells of the array are arranged such that applying an enable voltage to gates of the first transistors and the second transistors produces a unique bit string.

11. A method of manufacturing a memory device, comprising:

forming an array of cells, wherein each cell comprises;

a first transistor having a first gate oxide thickness;

a second transistor having a first gate oxide thickness greater than the first gate oxide thickness; and

a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor, and the reading circuit comprises a first inverter and a second inverter cross-coupled between the first transistor and the second transistor.

12. The method of claim 11, further comprising:

programming the first transistors to shift a distribution of threshold voltages of the first transistors from a first pre-BTI distribution to a first post-BTI distribution; and

programming the second transistors to shift a distribution of threshold voltages of the second transistors from a second pre-BTI distribution to a second post-BTI distribution.

13. The method of claim 12, wherein:

a mean of the first post-BTI distribution equals a mean of the second post-BTI distribution; and

a standard deviation of the first post-BTI distribution is different than a standard deviation of the second post-BTI distribution.

14. The method of claim 13, wherein:

a mean of the first pre-BTI distribution equals a mean of the second pre-BTI distribution; and

a standard deviation of the first pre-BTI distribution equals a standard deviation of the second pre-BTI distribution.

15. The method of claim 13, wherein:

a mean of the first pre-BTI distribution is comparable to a mean of the second pre-BTI distribution; and

a standard deviation of the first pre-BTI distribution is comparable to a standard deviation of the second pre-BTI distribution.

16. The method of claim 12, wherein:

the programming the first transistors is performed at a first programming voltage and a first programming temperature for a first programming time;

the programming the second transistors is performed at a second programming voltage and a second programming temperature for a second programming time; and

at least one of;

the second programming voltage is greater than the first programming voltage;

the second programming temperature is greater than the first programming temperature; and

the second programming time is greater than the first programming time.

17. The method of claim 11, further comprising:

programming the first transistors of the cells of the array using a first bias temperature instability (BTI) programming voltage; and

programming the second transistors of the cells of the array using a second bias temperature instability (BTI) programming voltage.

18. The method of claim 17, the first transistors of the cells of the array and the second transistors of the cells of the array have a same channel length and a same channel width.

19. The method of claim 18, wherein in each of the cells:

a drain of the first transistor is connected to an output of the first inverter and an input of the second inverter;

a drain of the second transistor is connected to an input of the first inverter and an output of the second inverter;

a source of the first transistor is connected to ground; and

a source of the second transistor is connected to ground.

20. The method of claim 11, further comprising reading a unique bit string from the cells of the array based on applying an enable voltage to gates of the first transistors and the second transistors.