Partial access mode for dynamic random access memory

• US 9,640,240 B2
• Filed: 01/30/2014
• Issued: 05/02/2017
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Riho, Yoshiro
• Primary Examiner(s): Parikh, Kalpit
• Application Number:
  US14/168,899
• Publication Number:
  US 20150149717A1
• Time in Patent Office: 1,188 Days
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2^N, the refresh time increases by more than 2^N as a consequence of the fact that the majority decision does better than averaging for the tail distribution of retention time. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required.

Claims

1. A device comprising:

a plurality of memory banks;

a controller controlling storage of data in cells of the plurality of memory banks;

a command decoder configured to provide an enable signal responsive to a partial access mode entry command signal;

a partial access mode code decoder configured to receive the enable signal, to receive a portion of address signals responsive to the enable signal, to convert the portion of the address signals into a plurality of code flag signals, and further configured to provide a copy operation control signal and the plurality of code signals; and

an address decoder circuit coupled to the controller, the address decoder circuit comprising;

at least one multi-bit decoding circuit comprising a plurality of switches, the plurality of switches including comprising a switch configured to select a plurality of word lines; and

a delay circuit configured to receive the portion of address signals and the copy operation control signal, and further configured to provide a delay signal when the copy operation control signal is active,

wherein the controller copies each bit of data stored in the plurality of memory banks that is to be preserved from 1 cell per bit to a plurality of cells per bit by a copy operation from the 1 cell connected with one word line to the plurality of cells connected with a plurality of respective word lines,

wherein the switch is configured to receive a corresponding code flag signal of the plurality of code flag signals and further configured to simultaneously select the plurality of word lines responsive to the corresponding code flag signal, and

wherein the switch is further configured to delay selection of the plurality of word lines responsive to the portion of address signals, further responsive to the corresponding code flag signal and the delay signal.

2. The device of claim 1, wherein the controller copying causes the effective retention time of each bit of data copied to be extended.

3. The device of claim 2, wherein the effective retention time of each bit of data copied is extended by a factor of 2^N.

4. The device of claim 1, wherein the controller copying causes the power consumption of the memory module to be reduced.

5. The device of claim 4, wherein the controller can reduce the power consumption of the device by copying each bit of data stored in the plurality of memory banks that is to be preserved from 1 cell per bit to 2^N cells per bit in both a normal operation mode and a self refresh operation mode.

6. The device of claim 1, wherein N=4.

7. The device of claim 1, wherein a portion of each memory bank of the plurality of memory banks is active when the memory module is in a self refresh mode of operation.

8. The device of claim 1, wherein the portion of address signals represents lower bits of a row address.

9. The device of claim 1, further comprising a refresh counter configured to select one or more bits based on the plurality of code flag signals,

wherein the partial access mode code decoder is further configured to provide a refresh control signal, and

wherein the refresh counter is configured to transmit pulses for instructing continuous copies operation responsive to the refresh control signal, and further configured to provide a stop signal instructing the continuous copies operation to the partial access mode code decoder and the address decoder circuit.

10. A method for managing storage of data in a device, the method comprising:

storing at least one bit of data in at least one cell of the device, wherein each bit of data is stored in a single cell of the device;

reading a portion of the at least one bit of data from a memory cell connected with one word line;

providing an enable signal responsive to a partial access mode entry command signal;

receiving the enable signal;

receiving a portion of address signals responsive to the enable signal;

converting the portion of the address signals into a plurality of code flag signals;

providing a copy operation control signal and the plurality of code flag signals;

receiving the portion of address signals and the copy operation control signal;

providing a delay signal when the received copy operation control signal is active;

receiving a corresponding code flag signal of the plurality of code flag signals by a switch, the corresponding code flag signal corresponds to a plurality of signals of the portion of address signals;

selecting a plurality of word lines coupled to a plurality of cells of the device simultaneously by the switch store the portion of the at least one bit of data;

writing the portion of the at least one bit of data into the plurality of cells,

wherein the selecting the plurality of word lines coupled to the plurality of cells of the device simultaneously to store the portion of the at least one bit of data further comprises;

delaying selection of the plurality of word lines responsive to the portion of address signals, further responsive to the corresponding code flag signal and the delay signal.

11. The method of claim 10, wherein the step of copying causes the effective retention time of each bit of data copied to be extended.

12. The method of claim 11, wherein the effective retention time of each bit of data copied is extended by a factor of 2^N.

13. The method of claim 10, wherein the step of copying allows the power consumption of the device to be reduced.

14. The method of claim 13, wherein the power consumption of the device can be reduced by the step of copying in both a normal operation mode and a self refresh operation mode.

15. The method of claim 10, wherein N=4.

16. The method of claim 10, wherein the at least one cell of the device is spread across a plurality of memory banks of the memory module, and a portion of each memory bank of the plurality of memory banks is active when the device is in a self refresh mode of operation.