Single-poly nonvolatile memory cell

• US 9,640,259 B2
• Filed: 11/20/2015
• Issued: 05/02/2017
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Ememory Technology Inc.
• Original Assignee: Ememory Technology Inc.
• Inventors: Li, Yi-Hung, Lai, Yen-Hsin, Lo, Ming-Shan, Huang, Shih-Chan
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): GARCES, NELSON Y
• Application Number:
  US14/946,796
• Publication Number:
  US 20160079251A1
• Time in Patent Office: 529 Days
• Field of Search: 257310-320
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0433 comprising cells containing a single floating gate transistor and one or more separate select transistors
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 2216/10 Floating gate memory cells with a single polysilicon layer
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/45 Ohmic electrodes
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/788 with floating gate H01L29/78391 takes precedence
• CPC Class Codes: H01L 29/7881 Programmable transistors with only two possible levels of programmation H01L29/7888 takes precedence
• CPC Class Codes: H01L 29/7882 charging by injection of carriers through a conductive insulator, e.g. Poole-Frankel conduction
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 41/35 : with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 41/60 : the control gate being a doped region, e.g. single-poly memory cell
• CPC Class Codes: H10B 43/35 : with cell select transistors, e.g. NAND

Abstract

A single-poly nonvolatile memory (NVM) cell includes a PMOS select transistor on a semiconductor substrate and a PMOS floating gate transistor series connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate and a gate oxide layer between the floating gate and the semiconductor substrate. A protector oxide layer covers and is indirect contact with the floating gate. A contact etch stop layer is disposed on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer.

Claims

1. A single-poly nonvolatile memory (NVM) cell, comprising:

a select transistor on a first well of a semiconductor substrate, wherein the select transistor comprises a select gate, a first gate oxide layer between the select gate and the semiconductor substrate, a first source/drain doping region in the first well, and a second source/drain doping region spaced apart from the first source/drain doping region;

a floating gate transistor on the first well serially connected to the select transistor, wherein the floating gate transistor comprises a floating gate, a second gate oxide layer between the floating gate and the semiconductor substrate, the second source/drain doping region commonly shared by the select transistor, and a third source/drain doping region spaced apart from the second source/drain doping region;

a first salicide layer on the first source/drain doping region;

a protector oxide layer covering and being in direct contact with the floating gate;

a contact etch stop layer on the protector oxide layer such that the floating gate is isolated from the contact etch stop layer by the protector oxide layer;

a first sidewall spacer provided on either sidewall of the select gate; and

a second sidewall spacer provided on either sidewall of the floating gate, wherein the protector oxide layer covers and is in direct contact with a top surface of the floating gate, surfaces of the second sidewall spacers, entire surface of the second source/drain doping region, and only a portion of the third source/drain doping region.

2. The single-poly NVM cell according to claim 1 wherein the first well is a medium-voltage N well.

3. The single-poly NVM cell according to claim 1 further comprising a second salicide layer on the third source/drain doping region, wherein the second salicide layer is kept a predetermined distance from an edge of a bottom of the second sidewall spacer.

4. The single-poly NVM cell according to claim 3 further comprising a third salicide layer on a top surface of the select gate.

5. The single-poly NVM cell according to claim 1 wherein no silicide layer is formed on a top surface of the floating gate.

6. The single-poly NVM cell according to claim 1 further comprising an inter-layer dielectric layer on the contact etch stop layer.

7. The single-poly NVM cell according to claim 6 further comprising a source line contact and a bit line contact in the inter-layer dielectric layer to electrically connected to the first source/drain doping region and the third source/drain doping region respectively.

8. The single-poly NVM cell according to claim 1 wherein the protector oxide layer is a silicon oxide layer.