Semiconductor device, pre-write program, and restoration program

• US 9,640,267 B2
• Filed: 03/31/2014
• Issued: 05/02/2017
• Est. Priority Date: 03/31/2014
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: Tani, Kunio
• Primary Examiner(s): Ho, Hoai V
• Application Number:
  US14/430,428
• Publication Number:
  US 20160260486A1
• Time in Patent Office: 1,128 Days
• Field of Search: 36518522
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/0475 comprising two or more independent storage sites which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/105 Circuits or methods for updating contents of nonvolatile memory, especially with 'security' features to ensure reliable replacement, i.e. preventing that old data is lost before new data is reliably written
• CPC Class Codes: G11C 16/107 Programming all cells in an array, sector or block to the same state prior to flash erasing
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/22 Safety or protection circuits preventing unauthorised or accidental access to memory cells
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 16/3477 Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
• CPC Class Codes: H05K 999/99 dummy group

Abstract

When a control circuit has received a first erase command, the control circuit controls performing a first pre-write process to allow a first storage device and a second storage device to have threshold voltages, respectively, both increased, and the control circuit thereafter controls performing an erase process to allow the first storage device and the second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level. When the control circuit has received a second erase command, the control circuit controls performing a second pre-write process to allow one of the first storage device and the second storage device to have its threshold voltage increased, and control circuit subsequently controls performing the erase process.

Claims

1. A semiconductor device comprising:

a memory array including a plurality of twin cells each formed of electrically rewritable, first and second storage devices holding binary data depending on a difference between a threshold voltage of said first storage device and a threshold voltage of said second storage device; and

a control circuit that controls erasing twin cell data held in said twin cells,

when said control circuit has received a first erase command, said control circuit controlling performing a first pre-write process to allow said first storage device and said second storage device to have their respective threshold voltages both increased, said control circuit thereafter controlling performing an erase process to allow said first storage device and said second storage device to have their respective threshold voltages both decreased to be smaller than a prescribed erase verify level, whereas when said control circuit has received a second erase command, said control circuit controlling performing a second pre-write process to allow one of said first storage device and said second storage device to have its threshold voltage increased, said control circuit thereafter controlling performing said erase process.

2. The semiconductor device according to claim 1, wherein:

when said control circuit has received a programming command, said control circuit increases the threshold voltage of one of said first storage device and said second storage device to exceed a first write verify voltage; and

when said control circuit has received said second erase command, said control circuit increases the threshold voltage of one of said first storage device and said second storage device to exceed a second write verify voltage, said second write verify voltage being larger than said first write verify voltage.

3. The semiconductor device according to claim 1, wherein when said control circuit has received said second erase command, said control circuit reads twin cell data from a prescribed twin cell in said memory array, and when said twin cell data indicates that the threshold voltage of said first storage device is larger than the threshold voltage of said second storage device, said control circuit increases the threshold voltage of said second storage device of said prescribed twin cell in said memory array and that of said second storage device of another twin cell in said memory array, whereas when said twin cell data indicates that the threshold voltage of said second storage device is larger than the threshold voltage of said first storage device, said control circuit increases the threshold voltage of said first storage device of said prescribed twin cell in said memory array and that of said first storage device of another twin cell in said memory array.

4. The semiconductor device according to claim 3, wherein:

when said control circuit has received said second erase command, said control circuit reads twin cell data from a twin cell in a leading area of a block to be erased in said memory array, and when said twin cell data indicates that the threshold voltage of said first storage device is larger than the threshold voltage of said second storage device, said control circuit increases the threshold voltage of said second storage device of each said twin cell in said memory array from said leading area through to an area of said block immediately preceding an intermediate area of said block, whereas when said twin cell data indicates that the threshold voltage of said second storage device is larger than the threshold voltage of said first storage device, said control circuit increases the threshold voltage of said first storage device of each said twin cell in said memory array from said leading area through to said area immediately preceding said intermediate area; and

said control circuit reads twin cell data from a twin cell in said intermediate area of said block to be erased in said memory array, and when said twin cell data indicates that the threshold voltage of said first storage device is larger than the threshold voltage of said second storage device, said control circuit increases the threshold voltage of said second storage device of each said twin cell in said memory array from said intermediate area through to a final area of said block, whereas when said twin cell data indicates that the threshold voltage of said second storage device is larger than the threshold voltage of said first storage device, said control circuit increases the threshold voltage of said first storage device of each said twin cell in said memory array from said intermediate area through to an area of said block immediately preceding said final area.

5. The semiconductor device according to claim 1, wherein when said control circuit has received said first erase command and thereafter, further received a restoration command, said control circuit reads twin cell data from said twin cell, and when said twin cell data indicates that the threshold voltage of said first storage device is larger than the threshold voltage of said second storage device, said control circuit increases the threshold voltage of said first storage device of said twin cell, whereas when said twin cell data indicates that the threshold voltage of said second storage device is larger than the threshold voltage of said first storage device, said control circuit increases the threshold voltage of said second storage device of said twin cell.

6. The semiconductor device according to claim 1, wherein:

a relationship in magnitude before the second pre-write process between the threshold of the first storage device and the threshold of the second storage device is not maintained after the erase process.