Mitigating hot electron program disturb

• US 9,640,273 B1
• Filed: 08/25/2016
• Issued: 05/02/2017
• Est. Priority Date: 08/25/2016
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Chen, Hong-Yan, Dong, Yingda, Zhao, Wei
• Primary Examiner(s): MAI, SON LUU
• Application Number:
  US15/247,746
• Time in Patent Office: 250 Days
• Field of Search: 36518502, 36518528
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3431 Circuits or methods to detect disturbed nonvolatile memory cells, e.g. which still read as programmed but with threshold less than the program verify threshold or read as erased but with threshold greater than the erase verify threshold, and to reverse the disturbance via a refreshing programming or erasing step

Abstract

Techniques are provided for preventing program disturb when programming a memory device. Hot electron injection program disturb is prevented or reduced. Voltage boosting of the NAND channel of a program inhibited NAND string may be controlled in a manner to reduce or eliminate a lateral electric field that could possibly accelerate electrons in the NAND channel. If the electrons gain enough energy due to the lateral electric field, they could potentially be injected into the charge storage region of a memory cell, thereby causing program disturb. Thus, the voltage boosting can prevent or reduce injection of hot electrons from the NAND channel to a charge storage region of a NAND memory cell during a programming operation, thereby preventing or reducing program disturb.

Claims

1. A three-dimensional (3D) non-volatile storage apparatus, comprising:

a plurality of bit lines;

a common source line;

a plurality of word lines;

a plurality of NAND strings of memory cells, each of the NAND strings having a channel, each of the NAND strings having a source end coupled to the common source line and a drain end coupled to a bit line of the plurality of bit lines, each of the memory cells associated with a word line of the plurality of word lines;

a control circuit in communication with the plurality of bit lines, the common source line, and the plurality of word lines, the control circuit configured to;

pre-charge a channel of a program inhibited NAND string during a pre-charge phase of a programming operation, the program inhibited NAND string having memory cells connected to a first set of word lines and a second set of word lines, the first set of word lines including a first unselected word line that neighbors a selected word line towards the source end, the second set of word lines including the selected word line and a second unselected word line that neighbors the selected word line towards the drain end;

during a boosting phase of the programming operation, initially increase a voltage on the first set of word lines by a greater amount than the control circuit initially increases a voltage on the second set of word lines;

finalize boosting voltages on the first set and the second set of word lines to respective final boosting voltages during the boosting phase of the programming operation; and

apply a programming voltage to the selected word line during a programming phase of the programming operation.

2. The 3D non-volatile storage apparatus of claim 1, wherein the control circuit being configured to initially increase a voltage on the first set of word lines by a greater amount than the control circuit initially increases a voltage on the second set of word lines comprises the control circuit being configured to:

begin to apply a boosting voltage to the first set of word lines prior to when the control circuit is configured to begin to apply a boosting voltage to the second set of word lines.

3. The 3D non-volatile storage apparatus of claim 1, wherein the control circuit being configured to initially increase a voltage on the first set of word lines by a greater amount than the control circuit initially increases a voltage on the second set of word lines comprises the control circuit being configured to:

ramp a boosting voltage on the first set of word lines at a faster rate than the control circuit is configured to ramp a boosting voltage on the second set of word lines.

4. The 3D non-volatile storage apparatus of claim 1, wherein the control circuit being configured to pre-charge a channel of a program inhibited NAND string during a programming operation comprises the control circuit configured to:

establish a first pre-charge voltage in the channel of the program inhibited NAND string adjacent a memory cell connected to the selected word line; and

establish a second pre-charge voltage in the channel of the program inhibited NAND string adjacent a memory cell connected to the first unselected word line, wherein the second pre-charge voltage is less than the first pre-charge voltage.

5. The 3D non-volatile storage apparatus of claim 1, wherein the first set includes all unselected word lines between the selected word line and the source end of the program inhibited NAND string.

6. The 3D non-volatile storage apparatus of claim 5, wherein the second set includes all unselected word lines between the selected word line and the drain end of the program inhibited NAND string.

7. The 3D non-volatile storage apparatus of claim 1, wherein the control circuit being configured to initially increase a voltage on the first set of word lines by a greater amount than the control circuit initially increases a voltage on the second set of word lines comprises the control circuit being configured to:

increase the voltage on the first unselected word line by more than the voltage increase on either the selected word line or the second selected word line by the time that a memory cell connected to the first selected word line becomes conductive.

8. A method of operating a three dimensional (3D) NAND memory device, the method comprising:

establishing one or more pre-charge voltages in a channel of a program inhibited 3D NAND string during a programming operation of a selected 3D NAND string, the program inhibited 3D NAND string having a source end coupled to a common source line and a drain end coupled to a bit line, the program inhibited 3D NAND string and the selected 3D NAND string are associated with a plurality of word lines that comprise a selected word line, a first unselected word line that neighbors the selected word line on a source side of the program inhibited 3D NAND string, and a second unselected word line that neighbors the selected word line on a drain side of the program inhibited 3D NAND string, establishing the one or more pre-charge voltages comprises applying a pre-charge voltage to the selected word line, the first unselected word line, and the second unselected word line;

boosting a channel potential of the program inhibited 3D NAND string during a channel boosting phase of the programming operation, boosting the channel potential comprising;

initially raising the voltage on the first unselected word line from the pre-charge voltage by a first voltage while initially raising the voltage on the selected word line and the second unselected word line from the pre-charge voltage by a second voltage that is less than the first voltage; and

continuing to raise the voltages on the first and the second unselected word lines to respective final boosting voltages; and

applying a programming voltage to the selected word line after the first and the second unselected word lines are at their respective final boosting voltages.

9. The method of claim 8, wherein initially raising the voltage on the first unselected word line from the pre-charge voltage by the first voltage while initially raising the voltage on the selected word line and the second unselected word line from the pre-charge voltage by the second voltage that is less than the first voltage comprises:

initiating application of a first boosting voltage to the first unselected word line prior to initiating application of a second boosting voltage to the selected word line and prior to initiating application of a third boosting voltage to the second unselected word line.

10. The method of claim 8, wherein initially raising the voltage on the first unselected word line from the pre-charge voltage by the first voltage while initially raising the voltage on the selected word line and the second unselected word line from the pre-charge voltage by the second voltage that is less than the first voltage comprises:

ramping a first boosting voltage to the first unselected word line at a faster rate than ramping a second boosting voltage to the selected word line and at a faster rate than ramping a third boosting voltage to the second unselected word line, including beginning to ramp the first boosting voltage, the second boosting voltage, and the third boosting voltage at approximately the same time.

11. The method of claim 8, wherein establishing the one or more pre-charge voltages in the channel of the program inhibited 3D NAND string during the programming operation of the selected 3D NAND string comprises:

establishing a voltage gradient in a portion of the channel of the program inhibited NAND string adjacent a memory cell connected to the selected word line and a memory cell connected to the first unselected word line.

12. The method of claim 8, wherein boosting the channel potential comprises:

initially raising the voltage on all unselected word lines between the selected word line and the source end of the program inhibited 3D NAND string by a greater amount than initially raising the voltage on either the selected word line or the second unselected word line.

13. The method of claim 12, wherein boosting the channel potential further comprises:

initially raising the voltage on all unselected word lines between the selected word line and the drain end of the program inhibited 3D NAND string by a lesser amount than initially raising the voltage on the first unselected word line.

14. The method of claim 8, wherein initially raising the voltage on the first unselected word line from the pre-charge voltage by the first voltage while initially raising the voltage on the selected word line and the second unselected word line from the pre-charge voltage by the second voltage that is less than the first voltage comprises:

raising the voltage on the first unselected word line by more than the voltage is raised on either the selected word line or the second selected word line by the time that a memory cell connected to the first selected word line becomes conductive.

15. A three-dimensional (3D) non-volatile storage apparatus, comprising:

a plurality of bit lines;

a common source line;

a plurality of conductive layers alternating with a plurality of insulating layers in a stack;

a plurality of NAND strings of memory cells, each NAND string extending through the stack, each of the NAND strings having a channel, each of the NAND strings having a drain end coupled to a bit line of the plurality of bit lines and a source end coupled to the common source line, each of the memory cells associated with a word line formed from at least a portion of one of the conductive layers;

a control circuit in communication with the plurality of bit lines, the common source line, and the word lines associate with the memory cells, the control circuit;

establishes one or more pre-charge voltages in the channel of a program inhibited NAND string during a programming operation of a selected NAND string that shares word lines with the program inhibited NAND string, the program inhibited NAND string having a first memory cell connected to a selected word line, a second memory cell that neighbors the first memory on the source end of the program inhibited NAND string, and a third memory cell that neighbors the first memory on the drain end of the program inhibited NAND string;

initially boosts a channel potential adjacent the second memory cell during a boosting phase of the programming operation by a first voltage and initially boosts a channel potential adjacent the first memory cell and the third memory cell by a second voltage that is less than the first voltage during the boosting phase;

finalizes boosting of the channel potential of the program inhibited NAND string during the boosting phase; and

applies a programming voltage to the selected word line connected to the first memory cell during a programming phase of the programming operation.

16. The 3D non-volatile storage apparatus of claim 15, wherein the second memory cell is non-conductive when the control circuit establishes the one or more pre-charge voltages, the control circuit initially boosts the channel potential adjacent the second memory cell during the boosting phase by the first voltage prior to a time at which the second memory cell becomes conductive during the boosting phase.

17. The 3D non-volatile storage apparatus of claim 15, wherein to initially boost the channel potential adjacent the second memory cell during the boosting phase of the programming operation by the first voltage and initially boost the channel potential adjacent the first memory cell and the third memory cell during the boosting phase by the second voltage the control circuit:

boosts the voltage in the channel adjacent to the second memory cell prior to boosting the voltage in the channel adjacent the first memory cell and prior to boosting the voltage in the channel adjacent the third memory cell.

18. The 3D non-volatile storage apparatus of claim 15, wherein to initially boost the channel potential adjacent the second memory cell during the boosting phase of the programming operation by the first voltage and initially boost the channel potential adjacent the first memory cell and the third memory cell during the boosting phase by the second voltage the control circuit:

boosts the voltage in the channel adjacent to the second memory cell at a faster rate than the control circuit boosts the voltage in the channel adjacent the first memory cell and at a faster rate than the control circuit boosts the voltage in the channel adjacent the third memory cell.

19. The 3D non-volatile storage apparatus of claim 15, wherein the one or more pre-charge voltages in the channel of the program inhibited NAND string comprise:

a first pre-charge voltage in the channel adjacent the second memory cell; and

a second pre-charge voltage in the channel adjacent the first memory cell, wherein the second pre-charge voltage is greater than the first pre-charge voltage.

20. A three-dimensional (3D) non-volatile storage apparatus, comprising:

a plurality of bit lines;

a common source line;

a plurality of word lines;

a plurality of NAND strings of memory cells, each of the NAND strings having a channel, each of the NAND strings having a source end coupled to the common source line and a drain end coupled to a bit line, each of the memory cells associated with a word line of the plurality of word lines;

means for applying a first voltage to a selected word line, a second voltage to a first unselected word line that neighbors the selected word line towards the source end, and a third voltage to a second unselected word line that neighbors the selected word line towards the drain end during a pre-charge phase of a programming operation, the selected word line and the first and second unselected word lines associated with both a selected NAND string and a program inhibited NAND string;

means for initially increasing the second voltage on the first unselected word line by a fourth voltage and initially increase the first voltage on the selected word line and the third voltage on the second unselected word line by less than the fourth voltage during a boosting phase of the programming operation;

means for finalizing boosting voltages on the first and the second unselected word lines to respective final boosting voltages during the boosting phase of the programming operation; and

means for applying a programming voltage to the selected word line while the respective final boosting voltages are on the first and the second unselected word lines during a programming phase of the programming operation.