Testability/manufacturing method to adjust output skew timing

• US 9,640,278 B1
• Filed: 12/10/2015
• Issued: 05/02/2017
• Est. Priority Date: 12/10/2015
• Status: Active Grant

• Current Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Xi, Xiaoming
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): Begum, Sultana
• Application Number:
  US14/964,953
• Time in Patent Office: 509 Days
• Field of Search: None
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports

Abstract

An apparatus includes an output driver circuit and a trimming circuit. The output driver circuit may be configured to (i) receive an input signal and a first control signal and (ii) generate an output signal. The output signal may be a delayed version of the input signal. A length of delay between the input signal and the output signal is determined in response to the first control signal. The trimming circuit may be configured to generate the first control signal in response to a second control signal. The trimming circuit is generally enabled to vary a value of the first control signal to minimize a phase difference between the output signal and an output clock signal.

Claims

1. An apparatus comprising:

an output driver circuit configured to (i) receive a data input signal, an input clock signal, and a first control signal and (ii) generate a data output signal and an output clock signal, wherein said data output signal is a delayed version of said data input signal and a length of delay between said data input signal and said data output signal is determined in response to said first control signal; and

a trimming circuit configured to be enabled during production testing by a command received by said apparatus from automated test equipment and to generate said first control signal in response to a second control signal, wherein said data input signal is generated during said production testing in response to a test pattern and a test clock received by said apparatus from said automated test equipment and said trimming circuit is enabled to (i) vary a value of said first control signal to minimize a phase difference between said data output signal and said output clock signal, (ii) determine whether the apparatus passes or fails said production test based upon a trimming result, and (iii) notify the automated test equipment about the pass or fail status of the apparatus under test.

2. The apparatus according to claim 1, wherein said data output signal drives a line of an output address and command bus connected to a plurality of memory chips of a double data rate (DDR) memory module.

3. The apparatus according to claim 2, wherein said DDR memory module comprises a double data rate fourth generation (DDR4) dual in-line memory module (DIMM).

4. The apparatus according to claim 1, wherein said trimming circuit is further configured to:

determine whether the phase difference between said data output signal and said output clock signal meets a predefined criteria;

store said value of said first control signal in a one time programmable memory when said phase difference meets the predefined criteria; and

indicate a failure condition when said phase difference does not meet the predefined criteria.

5. The apparatus according to claim 4, wherein the predefined criteria comprise a double data rate fourth generation (DDR4) output address and control bus output skew timing specification.

6. The apparatus according to claim 4, wherein the predefined criteria comprise an output skew within +/−

50 picoseconds.

7. The apparatus according to claim 1, wherein said trimming circuit comprises a state machine configured to vary the value of said first control signal to minimize said phase difference between said data output signal and said output clock signal to within a single gate delay of said output clock signal.

8. The apparatus according to claim 1, wherein said output driver circuit comprises a programmable delay line configured to vary the length of delay between said data input signal and said data output signal in response to said first control signal.

9. The apparatus according to claim 8, wherein said programmable delay line comprises:

a plurality of delay stages connected in series; and

a multiplexer connected to said plurality of delay stages and controlled by said first control signal.

10. The apparatus according to claim 1, further comprising an error detection circuit configured to generate an error count in response to said data output signal and said data output clock signal having a phase difference greater than a predetermine value, wherein said trimming circuit is further configured to read the error count in one state and clear the error count in another state.

11. The apparatus according to claim 10, wherein said error detection circuit comprises a register configured to load a predetermined value in response to a logical combination of said data output signal and said output clock signal.

12. The apparatus according to claim 1, wherein said trimming circuit is further configured to minimize a phase difference between a plurality of data output signals and said output clock signal.

13. The apparatus according to claim 1, wherein said apparatus is part of a registered clock driver.

14. The apparatus according to claim 1, wherein said trimming circuit is configured to notify said automated test equipment about the pass or fail status of the apparatus by setting a status register based upon the trimming results.

15. A method of adjusting output skew timing of an output driver circuit comprising the steps of:

enabling a trimming circuit generate a first control signal during production testing in response to a command received from automated test equipment;

generating a data input signal to said driver circuit during said production testing in response to a test pattern and a test clock received from said automated test equipment;

generating a data output signal and an output clock signal using said output driver circuit, wherein said data output signal is a delayed version of said data input signal and a length of delay is determined in response to said first control signal;

varying a value of said first control signal until a phase difference between said data output signal and said output clock signal is minimized;

determining whether the output driver circuit passes or fails said production test based upon a trimming result; and

notifying the automated test equipment about the pass or fail status of the output driver circuit under test.

16. The method according to claim 15, further comprising:

determining whether the phase difference meets a predefined criteria;

when the phase difference meets the predefined criteria, storing said value in a memory; and

when the phase difference does not meet the predefined criteria, indicating a failure condition.

17. The method according to claim 16, wherein the predefined criteria comprise a double data rate fourth generation (DDR4) output address and control bus output skew specification.

18. The method according to claim 17, wherein the predefined criteria comprise an output skew within +/−

50 picoseconds.

19. The method according to claim 15, wherein

said trimming circuit is configured to notify said automated test equipment about the pass or fail status of the apparatus by setting a status register based upon the trimming results.

20. An apparatus comprising:

means for (i) receiving a data input signal, an input clock signal, and a first control signal and (ii) generating an output clock signal and data output signal, wherein said data output signal is a delayed version of said data input signal and a length of delay between said data input signal and said data output signal is determined in response to said first control signal; and

means for generating said first control signal in response to a second control signal, wherein (i) said data input signal is generated during a production testing in response to a test pattern and a test clock received by said apparatus from automated test equipment and (ii) said means for generating said first control signal is configured to be enabled during said production testing by a command received by said apparatus from said automated test equipment, and to vary a value of said first control signal to minimize a phase difference between said data output signal and said output clock signal, to determine whether the apparatus passes or fails said production test based upon a trimming result, and to notify said automated test equipment about the pass or fail status of the apparatus under test.