Power domain aware insertion methods and designs for testing and repairing memory

• US 9,640,280 B1
• Filed: 11/02/2015
• Issued: 05/02/2017
• Est. Priority Date: 11/02/2015
• Status: Expired due to Fees

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Inventors: Arora, Puneet, Kaushik, Navneet, Gregor, Steven Lee, Card, Norman
• Primary Examiner(s): Levin, Naum B
• Application Number:
  US14/930,316
• Time in Patent Office: 547 Days
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G11C 29/10 Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
• CPC Class Codes: G11C 29/12 Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
• CPC Class Codes: G11C 29/38 Response verification devices

Abstract

Aspects of the present disclosure involve insertion of power domain aware memory testing logic into integrated circuit designs to enable efficient testing of the memories embedded therein. In example embodiments, each power domain of the integrated circuit, and the memories included therein, are associated with dedicated test data register (TDR) set and instruction set. Each instruction set causes memory test logic circuitry in the integrated circuit to test the memories included in the corresponding power domain in parallel. Once testing of memories within a particular power domain is over, the test circuitry tests memories belonging to another power domain in parallel, and so on.

Claims

1. A system comprising:

an integrated circuit comprising a plurality of power domains, each power domain including a plurality of memories; and

a memory test logic circuitry embedded in the integrated circuit, the memory test logic circuitry including a memory test logic and a plurality of test data register (TDR) sets, the memory test logic including a first instruction set associated with a first power domain of the integrated circuit and a second instruction set associated with a second power domain of the integrated circuit, the first instruction set, when executed by the test logic circuit, causing the memory test logic circuitry to;

evaluate a first set of memories included in the first power domain, and store a first result data set in a first TDR set based on a result of the evaluation, the first TDR set corresponding to the first power domain, and the second instruction set, when executed by the memory test logic circuitry, causing the memory test logic circuitry to;

evaluate a second set of memories included in the second power domain, and store a second result data set in a second TDR set based on a result of the evaluation of the second set of memories, the second TDR set corresponding to the second power domain of the integrated circuit.

2. The system of claim 1, wherein the memory test logic circuitry further includes a test access port (TAP) configured to receive an input control signal, the control signal instructing the memory test logic circuitry to execute the first and second instruction sets.

3. The system of claim 1, wherein the input control signal causes the test logic circuit to serially execute the first and second instruction sets.

4. The system of claim 1, wherein the first power domain is active during execution of the first instruction set.

5. The system of claim 4, wherein the second power domain is inactive during execution of the first instruction set.

6. The system of claim 1, wherein the first instruction set causes the first set of memories to be evaluated in parallel.

7. The system of claim 1, wherein the first TDR set associated with the first power domain is isolated from the second TDR set associated with the second power domain.

8. The system of claim 1, wherein the test data logic further includes a third instruction set associated with a third power domain, the third instruction set, when executed by the memory test logic circuitry, causes the test data logic circuitry to perform operations comprising:

evaluate a third set of memories included in the third power domain, and store a third test data set in a third test data register based on a result of the evaluation of the third set of memories, the third test data register corresponding to the third power domain of the integrated circuit.

9. A method comprising:

providing, using one or more processors, a input control signal to a memory test logic circuitry of an integrated circuit, the integrated circuit including a plurality of power domains, the input control signal causing the memory test logic circuitry to execute a memory test logic included in the memory test logic circuitry, the memory test logic including a first instruction set associated with a first power domain of the integrated circuit and a second instruction set associated with a second power domain of the integrated circuit, the first instruction set, when executed by the memory test logic circuitry, causing the memory test logic circuitry to;

evaluate a first set of memories included in the first power domain, and store a first result data set in a first TDR set based on a result of the evaluation, the first TDR set corresponding to the first power domain, and the second instruction set, when executed by the memory test logic circuitry, causing the memory test logic circuitry to;

evaluate a second set of memories included in the second power domain, and store a second result data set in a second TDR set based on a result of the evaluation of the second set of memories, the second TDR set corresponding to the second power domain of the integrated circuit.

10. The method of claim 9, further comprising:

reading, via the test access port, the first set of result data from the first test data register; and

reading, via the test access port, the second set of result data from the second test data register.

11. The method of claim 9, wherein the input control signal causes the memory test logic circuitry to serially execute the first and second instruction sets.

12. The method of claim 11, wherein the test logic circuitry serially executing the first and second instructions sets causes the memory test logic circuitry to evaluate the first and second set of memories in series.

13. The method of claim 9, herein the first power domain is active during execution of the first instruction set.

14. The method of claim 13, wherein the second power domain is inactive during execution of the first instruction set.

15. The method of claim 9, wherein the first instruction set causes memories within the first set of memories to be evaluated in parallel.

16. The method of claim 13, wherein the first TDR set associated with the first power domain is isolated from the second TDR set associated with the second power domain.

17. The method of claim 9, wherein the test logic further includes a third instruction set associated with a third power domain, the third instruction set, when executed by the memory test logic circuitry, causes the memory test logic circuitry to perform operations comprising:

evaluate a third set of memories included in the third power domain, and a third test data set in a third test data register based on a result of the evaluation of the second set of memories, the second test data register corresponding to the second power domain of the integrated circuit.

18. A method comprising:

defining, using one or more processors of a machine, a memory test logic including a first instruction set associated with a first power domain of an integrated circuit and a second instruction set associated with a second power domain of the integrated circuit, the integrated circuit including a memory test logic circuitry, the first instruction set, when executed by the memory test logic circuitry, causing the memory test logic circuitry to;

evaluate a first set of memories included in the first power domain, and store a first result data set in a first test data register (TDR) set based on a result of the evaluation, the first TDR set corresponding to the first power domain, and the second instruction set, when executed by the memory test logic circuitry, causing the memory test logic circuitry to;

evaluate a second set of memories included in the second power domain, and store a second result data set in a second TDR set based on a result of the evaluation of the second set of memories, the second TDR set corresponding to the second power domain of the integrated circuit; and

inserting the memory test logic into the memory test logic circuitry of the integrated circuit.

19. The method of claim 18, wherein the memory test logic circuitry serially executes the first and second instruction sets such that the memory test logic circuitry evaluates the first and second set of memories in series.

20. The method of claim 18, wherein the first and second TDR sets are separate and distinct.