Semiconductor devices and methods of fabricating semiconductor devices

• US 9,640,443 B2
• Filed: 05/13/2016
• Issued: 05/02/2017
• Est. Priority Date: 12/27/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Kug-Hwan, Lee, Jong-Ho, Kim, Woo-Hee, Lee, Nae-In
• Primary Examiner(s): Stark, Jarrett
• Assistant Examiner(s): DINKE, BITEW A
• Application Number:
  US15/154,032
• Publication Number:
  US 20160276225A1
• Time in Patent Office: 354 Days
• CPC Class Codes: H01L 21/28202 in a nitrogen-containing ambient, e.g. nitride deposition, growth, oxynitridation, NH3 nitridation, N2O oxidation, thermal nitridation, RTN, plasma nitridation, RPN
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/4958 with a multiple layer structure
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: H10B 10/18 Peripheral circuit regions

Abstract

Semiconductor devices are provided. A semiconductor device includes a substrate including first through fourth areas. Moreover, first through fourth gate insulating layers are on the first through fourth areas, respectively. Amounts of work function control materials in the first through fourth gate insulating layers, nitrogen concentrations in the first through fourth gate insulating layers, and/or thicknesses of the first through fourth gate insulating layers vary among the first through fourth gate insulating layers. Methods for fabricating semiconductor devices are also provided.

Claims

1. A method of fabricating a semiconductor device, the method comprising:

forming a gate insulating layer on first through fourth areas of a substrate;

providing a first concentration of nitrogen to portions of the gate insulating layer that are formed on the first and second areas of the substrate, and a second concentration of nitrogen to portions of the gate insulating layer that are formed on the third and fourth areas of the substrate, wherein the second concentration of nitrogen comprises a different concentration from the first concentration of nitrogen;

forming a work function control material layer on the first through fourth areas of the substrate;

forming a capping layer on the work function control material layer, wherein the capping layer is formed to a first thickness on the first and third areas of the substrate, and to a second thickness that is different from the first thickness, on the second and fourth areas of the substrate; and

annealing the substrate.

2. The method of claim 1, wherein providing the first and second concentrations of nitrogen to the gate insulating layer comprises:

forming a mask on the third and fourth areas of the substrate;

then

nitriding the portions of the gate insulating layer formed on the first through fourth areas of the substrate.

3. The method of claim 1,

wherein forming the capping layer comprises forming first and second capping layers that are stacked sequentially,

wherein the first capping layer comprises the different first and second thicknesses, and

wherein the second capping layer is formed to a third thickness on the first and third areas of the substrate that is equally thick as a fourth thickness of the second capping layer on the second and fourth areas of the substrate.

4. The method of claim 3, wherein the first and second capping layers comprise a nitride layer and a semiconductor material, respectively.

5. The method of claim 4, wherein the first and second capping layers comprise titanium nitride (TiN) and silicon (Si), respectively.

6. The method of claim 1,

wherein forming the capping layer comprises forming first and second capping layers that are stacked sequentially,

wherein a third thickness of portions of the first capping layer formed on the first and third areas of the substrate is equally thick as a fourth thickness of portions of the first capping layer formed on the second and fourth areas of the substrate, and

wherein the method further comprises removing the second capping layer from the first and third areas of the substrate but not the second and fourth areas of the substrate.

7. The method of claim 1,

wherein the work function control material layer comprises a work function control material, and

wherein the work function control material comprises any one of lanthanum and aluminum.

8. The method of claim 7,

wherein forming the gate insulating layer comprises forming first through fourth gate insulating layers on the first through fourth areas of the substrate, respectively,

wherein after annealing the substrate, a first amount of the work function control material in each of the first and second gate insulating layers is different from a second amount of the work function control material in each of the third and fourth gate insulating layers, and

wherein third and fourth thicknesses of the first and third gate insulating layers, respectively, are different from fifth and sixth thicknesses of the second and fourth gate insulating layers, respectively.

9. The method of claim 1, wherein forming the gate insulating layer on the first through fourth areas comprises:

forming an interlayer insulating film comprising first through fourth trenches formed on the first through fourth areas, respectively; and

forming the gate insulating layer in the first through fourth trenches.

10. A method of fabricating a semiconductor device, the method comprising:

forming a gate insulating layer on first through fourth areas of a substrate;

providing a first concentration of nitrogen to portions of the gate insulating layer that are formed on the first and second areas of the substrate, and a second concentration of nitrogen to portions of the gate insulating layer that are formed on the third and fourth areas of the substrate, wherein the second concentration of nitrogen comprises a different concentration from the first concentration of nitrogen;

forming a blocking layer on the gate insulating layer;

removing the blocking layer from the second and fourth areas of the substrate, but not the first and third areas of the substrate;

forming a work function control material layer on the first through fourth areas of the substrate;

forming a capping layer on the work function control material layer; and

annealing the substrate.

11. The method of claim 10, wherein the blocking layer comprises a nitride layer.