Power amplifier package and method thereof

• US 9,640,457 B2
• Filed: 01/20/2015
• Issued: 05/02/2017
• Est. Priority Date: 01/20/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Chung-Hao, Hsieh, Jeng-Shien, Wang, Chuei-Tang
• Primary Examiner(s): Choe, Henry
• Application Number:
  US14/600,555
• Publication Number:
  US 20160211214A1
• Time in Patent Office: 833 Days
• Field of Search: 330307, 330124 R, 330295
• CPC Class Codes: H01L 21/568 Temporary substrate used as encapsulation process aid H01L21/4832 and H01L21/566 take precedence
• CPC Class Codes: H01L 2223/6644 Packaging aspects of high-frequency amplifiers
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/18 High density interconnect [HDI] connectors; Manufacturing methods related thereto
• CPC Class Codes: H01L 2224/24137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/92244 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/3738 Semiconductor materials
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect

Abstract

A device is provided, which includes a wiring structure including a first surface and a second surface opposite the first surface. The device also includes a first semiconductor die on the first surface of the wiring structure where the first semiconductor die includes first power amplifier unit. The device further includes a second semiconductor die on the first surface of the wiring structure where the second semiconductor has a second power amplifier unit and is spaced apart from the first semiconductor die. In addition, the device includes a first input port at the second surface of the wiring structure, and a first conductor in the wiring structure to electrically connect the first input port to the first semiconductor die and the second semiconductor die.

Claims

1. A device, comprising:

a wiring structure including a first surface and a second surface opposite the first surface;

a first semiconductor die on the first surface of the wiring structure, the first semiconductor die including a first power amplifier unit;

a second semiconductor die on the first surface of the wiring structure, the second semiconductor including a second power amplifier unit and being spaced apart from the first semiconductor die;

a first input port at the second surface of the wiring structure;

a first conductor, in the wiring structure, configured to electrically connect the first input port to the first semiconductor die and the second semiconductor die; and

a first output port at the second surface of the wiring structure; and

a second conductor, in the wiring structure, configured to connect the first semiconductor die and the second semiconductor die to the first output port,

wherein the second conductor provides a first transmission path for delivering power from the first semiconductor die to the first output port, and a second transmission path for delivering power from the second semiconductor die to the first output port.

2. The device according to claim 1, wherein the first conductor provides a third transmission path for delivering power from the first input port to the first semiconductor die, and a fourth transmission path for delivering power from the first input port to the second semiconductor die.

3. The device according to claim 2 further comprising a first power splitter disposed at the joint of the third transmission path and the fourth transmission path.

4. The device according to claim 1 further comprising a first power combiner disposed at the joint of the first transmission path and the second transmission path.

5. The device according to claim 1 further comprising:

a third conductor, in the wiring structure, configured to connect a second input port to the first semiconductor die and the second semiconductor die, the third conductor providing a fifth transmission path for delivering power from the second input port to the first semiconductor die, and a sixth transmission path for delivering power from the second input port to the second semiconductor die.

6. The device according to claim 1 further comprising:

a fourth conductor, in the wiring structure, configured to connect the first semiconductor die and the second semiconductor die to a second output port at the second surface of the wiring structure, the fourth conductor providing a seventh transmission path for delivering power from the first semiconductor die to the second output port, and an eighth transmission path for delivering power from the fourth semiconductor die to the second output port.

7. The device according to claim 1 further comprising:

a third semiconductor die on the first surface of the wiring structure, the third semiconductor die including a third power amplifier unit; and

a fourth semiconductor die on the first surface of the wiring structure, the fourth semiconductor die including a fourth power amplifier unit and being spaced apart from the third semiconductor die.

8. The device according to claim 7, wherein the first conductor further provides a fifth transmission path for delivering power from the first input port to the third semiconductor die, and a sixth transmission path for delivering power from the first input port to the fourth semiconductor die.

9. The device according to claim 8 further includes a second power splitter disposed at the joint of the fifth transmission path and the sixth transmission path.

10. The device according to claim 1 further comprising a thermal conductive layer on the first semiconductor die and the second semiconductor die.

11. The device according to claim 10 further comprising a thermal conductive column between the thermal conductive layer and the wiring structure.

12. A device, comprising:

a wiring structure;

a first semiconductor die, on the wiring structure, including a first power amplifier unit;

a second semiconductor die, on the wiring structure, including a second power amplifier unit and being spaced apart from the first semiconductor die;

a thermal conductive layer on the first semiconductor die and the second semiconductor die,

wherein the wiring structure further comprises;

a first output port disposed on a surface opposite the first semiconductor die and the second semiconductor die; and

a first conductor connecting the first semiconductor die and the second semiconductor die to the first output port, wherein the first conductor provides a first transmission path for delivering power from the first semiconductor die to the first output port, and a second transmission path for delivering power from the second semiconductor die to the first output port.

13. The device according to claim 12, wherein the thermal conductive layer includes silicon-based material.

14. The device according to claim 12 further comprising a thermal conductive column between the thermal conductive layer and the wiring structure.

15. The device according to claim 12 further comprising a thermal interface layer between the thermal conductive layer and the first semiconductor die and the second semiconductor die.

16. A method, comprising:

providing a carrier;

attaching a first semiconductor die and a second semiconductor die on the carrier, the first semiconductor die including a first power amplifier unit, the second semiconductor die including a second power amplifier unit and being spaced apart from the first semiconductor die;

encapsulating the first semiconductor die and the second semiconductor die in an encapsulating layer; and

forming a wiring structure on the encapsulating layer, the wiring structure comprising;

an input port and an output port, the input port and the output port being disposed on a surface opposite the first semiconductor die and the second semiconductor die;

a first conductor configured to electrically connect the input port to the first semiconductor die and the second semiconductor die; and

a second conductor configured to electrically connect the first semiconductor die and the second semiconductor die to the output port,

wherein the second conductor provides a first transmission path for delivering power from the first semiconductor die to the output port, and a second transmission path for delivering power from the second semiconductor die to the output port.

17. The method according to claim 16, wherein the carrier includes a thermally conductive material.

18. The method according to claim 16, before encapsulating the first semiconductor die and the second semiconductor die, further comprising:

forming a thermal conductive column on the carrier.