Stacked microelectronic devices

• US 9,640,458 B2
• Filed: 08/27/2014
• Issued: 05/02/2017
• Est. Priority Date: 08/19/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ye, Seng Kim Dalson, Chong, Chin Hui, Lee, Choon Kuan, Lee, Wang Lai, Said, Roslan Bin
• Primary Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US14/470,831
• Publication Number:
  US 20150137364A1
• Time in Patent Office: 979 Days
• Field of Search: 257686, 257E25013, 257E25018, 257E25021, 257E25027, 257E25016, 438 74, 438107, 438109, 438613
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16055 being circular or elliptic
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73215 Layer and wire connectors
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2224/73257 Bump and wire connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/83 using a layer connector
• CPC Class Codes: H01L 2224/85 using a wire connector
• CPC Class Codes: H01L 2224/92147 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92247 the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2225/1023 : the support being an insulating substrate
• CPC Class Codes: H01L 2225/1041 : Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 : Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 2225/1088 : Arrangements to limit the height of the assembly
• CPC Class Codes: H01L 23/3128 : the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/49833 : the chip support structure consisting of a plurality of insulating substrates
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 25/117 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01052 : Tellurium [Te]
• CPC Class Codes: H01L 2924/0106 : Neodymium [Nd]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15184 : in different layers of the multilayer substrate
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/15331 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/1815 : Shape
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices are described herein. In one embodiment, a set of stacked microelectronic devices includes (a) a first microelectronic die having a first side and a second side opposite the first side, (b) a first substrate attached to the first side of the first microelectronic die and electrically coupled to the first microelectronic die, (c) a second substrate attached to the second side of the first microelectronic die, (d) a plurality of electrical couplers attached to the second substrate, (e) a third substrate coupled to the electrical couplers, and (f) a second microelectronic die attached to the third substrate. The electrical couplers are positioned such that at least some of the electrical couplers are inboard the first microelectronic die.

Claims

1. A stacked microelectronic device, comprising:

a first interposer substrate having a first side and a second side facing away from the first side;

a microelectronic die having an active side and a backside, wherein the microelectronic die includes a plurality of terminals arranged in an array on the active side, and wherein the backside is attached to the first side of the first interposer substrate, and wherein the microelectronic die has a first lateral surface;

a plurality of interconnect elements positioned corresponding to and electrically coupled to the plurality of terminals;

a second interposer substrate having a first side facing away from the microelectronic die, a second side facing the microelectronic die, a plurality of contacts on the second side corresponding to the plurality of terminals, and a circuitry extending through the second interposer and electrically coupled to the contacts on the second side, and wherein the microelectronic die is positioned between the first and second interposer substrates, and wherein the first interposer substrate is electrically coupled to the microelectronic die via the plurality of terminals, the plurality of contacts of the second interposer substrate, the plurality of interconnect elements, and the circuitry through the second interposer, and wherein the second interposer substrate has a second lateral surface; and

an underfill material positioned between the microelectronic die and the second interposer substrate, wherein the underfill material at least partially bears stress between the microelectronic die and the second interposer substrate, wherein the underfill material is formed with an outmost surface, and wherein the outmost surface is substantially flush with the first lateral surface and the second lateral surface.

2. The device of claim 1, further comprising:

a casing around a perimeter portion of the first side of the second interposer substrate and an opening through the casing through which a central region of the first side of the second interposer substrate is exposed.

3. The device of claim 1, wherein the microelectronic die is a first microelectronic die, the plurality of terminals are first terminals, the plurality of interconnect elements are first interconnect elements, and the plurality of contacts are first contacts, and wherein the device further comprises:

a third interposer substrate having a first side and a second side facing away from the first side, the second side facing the second interposer substrate;

a second microelectronic die having a plurality of second terminals arranged corresponding to the array of terminals of the first microelectronic die, wherein the second microelectronic die is attached to the first side of the second interposer substrate;

a plurality of second interconnect elements electrically coupled to the plurality of second terminals;

a fourth interposer substrate attached to the second microelectronic die, wherein the fourth interposer substrate includes a plurality of second contacts, and wherein the second microelectronic die is positioned between the third and fourth interposer substrates, wherein the third interposer substrate is electrically coupled to the second microelectronic die via the plurality of second contacts and the plurality of second interconnect elements; and

an electrical coupling between the second and third interposer substrates.

4. The device of claim 3, wherein the electrical coupling between the second and third interposer substrates includes an array of solderballs.

5. The device of claim 3, wherein the fourth interposer substrate has a first side facing away from the second microelectronic die and a second side opposite from the first side, and wherein the device further comprises:

a casing around a perimeter portion of the first side of the fourth interposer substrate having an opening through which a central region of the first side of the fourth interposer substrate is exposed.

6. The device of claim 1, further comprising:

a first contact positioned on the first side of the second interposer substrate and configured to electrically couple to a first corresponding contact of the first interposer substrate; and

a second contact positioned on the first side of the second interposer substrate and configured to electrically couple to a second corresponding contact of the first interposer substrate.

7. The device of claim 6, further comprising:

a plurality of pads positioned on the first side of the second interposer substrate and configured to electrically couple to the first contact.

8. The device of claim 6, wherein the second interposer substrate includes:

a conductive trace electrically coupling the first contact to a corresponding one of the contacts positioned on the second side of the second interposer substrate.

9. The device of claim 6, wherein the second interposer substrate includes:

a conductive trace electrically coupling the second contact to a corresponding pad positioned on the first side of the second interposer substrate.

10. The device of claim 1, further comprising a wire-bond for electrically connecting the first interposer substrate and the second interposer substrate.

11. The device of claim 1, wherein the first interposer substrate includes a slot extending between the first side of the first interposer substrate and the second side of the first interposer substrate.

12. The device of claim 1, further comprising a wire-bond for electrically connecting the microelectronic die and the first interposer substrate.

13. The device of claim 12, wherein:

the circuitry through the second interposer substrate is coupled to a plurality of first contacts at the first side of the second interposer substrate;

the first contacts at the first side of the second interposer substrate are electrically coupled to at least one contact at the second side of the second interposer substrate; and

the wire-bond is connected to the first interposer substrate and one of the first contacts at the first side of the second interposer substrate.

14. The device of claim 1, wherein the first interposer substrate is electrically coupled to the second interposer substrate by at least one wire-bond.