Leadless electronic packages for GaN devices

• US 9,640,471 B2
• Filed: 02/22/2016
• Issued: 05/02/2017
• Est. Priority Date: 02/24/2015
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel M.
• Primary Examiner(s): Ho, Anthony
• Application Number:
  US15/050,338
• Publication Number:
  US 20160247751A1
• Time in Patent Office: 435 Days
• Field of Search: 257 76
• CPC Class Codes: H01L 21/561 Batch processing
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05014 being square
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0612 Layout
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45139 Silver (Ag) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/45147 Copper (Cu) as principal constituent
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/4814 the wire connector connecting to a bonding area protruding from the surface
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48479 on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/85051 : Forming additional members, e.g. for "wedge-on-ball", "ball-on-wedge", "ball-on-ball" connections
• CPC Class Codes: H01L 2224/85186 : connecting first outside the semiconductor or solid-state body, i.e. off-chip, reverse stitch
• CPC Class Codes: H01L 23/3107 : the device being completely enclosed
• CPC Class Codes: H01L 23/3114 : the device being a chip scale package, e.g. CSP
• CPC Class Codes: H01L 23/49503 : characterised by the die pad
• CPC Class Codes: H01L 23/49541 : Geometry of the lead-frame
• CPC Class Codes: H01L 23/49548 : Cross section geometry H01L23/49562 takes precedence
• CPC Class Codes: H01L 23/49562 : for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/49575 : Assemblies of semiconductor devices on lead frames
• CPC Class Codes: H01L 23/49589 : Capacitor integral with or on the leadframe
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/04 : the devices not having separate containers
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/072 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/1033 : Gallium nitride [GaN]
• CPC Class Codes: H01L 2924/1304 : Transistor
• CPC Class Codes: H01L 2924/1306 : Field-effect transistor [FET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1425 : Converter
• CPC Class Codes: H01L 2924/1426 : Driver
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19105 : in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H02M 3/158 : including plural semiconductor devices as final control devices for a single load

Abstract

Leadless electronic packages for GaN-based half bridge power conversion circuits have low inductance internal and external connections, high thermal conductivity and a large separation between external connections for use in high voltage power conversion circuits. Some electronic packages employ “L” shaped power paths and internal low impedance die to die connections. Further embodiments employ an insulative substrate disposed within the electronic package for efficient power path routing and increased packaging density.

Claims

1. An integrated half-bridge component comprising:

a first semiconductor die mounted to a first die pad and including a first power transistor having a first source terminal and a first drain terminal, wherein the first source terminal is electrically coupled to the first die pad;

a second semiconductor die mounted to a second die pad and including a second power transistor having a second source terminal and a second drain terminal, wherein the second source terminal is electrically coupled to the second die pad;

an electrically insulative encapsulant formed around the first and the second semiconductor dies; and

wherein the integrated half-bridge component has an external ground connection formed by the first die pad, an external switch node connection formed by the second die pad and an external V_in connection that is coupled to a drain of the second semiconductor die.

2. The integrated half-bridge component of claim 1 further comprising a gap having a distance of at least 1.5 mm disposed between the first die pad and the second die pad.

3. The integrated half-bridge component of claim 1 wherein the first and the second semiconductor dies are GaN-based.

4. The integrated half-bridge component of claim 1 wherein the first semiconductor die has a top surface including the first source and the first drain terminal and a bottom surface that is attached to the first die pad.

5. The integrated half-bridge component of claim 1 wherein the first drain terminal is electrically coupled to the second die pad.

6. The integrated half-bridge component of claim 5 further comprising power connections disposed on a bottom surface of the integrated half-bridge component including a ground connection, a switch node connection and a V_in connection.

7. The integrated half-bridge component of claim 6 wherein the power connections are arranged in an “

L”

shaped pattern with the ground connection forming a first leg, the switch node connection forming a corner and the V_in connection forming a second leg.

8. The integrated half-bridge component of claim 6 wherein the power connections are arranged in a linear pattern wherein the ground connection is followed by the switch node connection that is followed by the V_in connection.

9. The integrated half-bridge component of claim 1 wherein the first semiconductor die includes a first level shift circuit that is electrically coupled to a level shift receiver terminal on the second semiconductor die.

10. The integrated half-bridge component of claim 9 wherein the level shift receiver terminal is coupled to a signal modulator that is coupled to a second power transistor drive circuit.

11. The integrated half-bridge component of claim 9 wherein the first level shift circuit is coupled to a gate drive terminal on the second semiconductor die using a die to die wirebond.

12. The integrated half-bridge component of claim 11 wherein the die to die wirebond is formed using a bond stitch on ball attachment.

13. An electronic power conversion component comprising:

an electrically conductive package base comprising a plurality of leads and first and second die pads;

a first GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the first die pad and wherein the top surface includes a first power transistor having a first source terminal and a first drain terminal, wherein the first source terminal is electrically coupled to the first die pad;

a second GaN-based die having a top surface opposite a bottom surface, wherein the bottom surface is attached to the second die pad and wherein the top surface includes a second power transistor having a second source terminal and a second drain terminal, wherein the second source terminal is electrically coupled to the second die pad;

one or more conductors electrically coupling at least one of the plurality of leads to the first GaN-based die; and

an encapsulant formed over the first and second GaN-based dies and at least a top surface of the electrically conductive package base.

14. The electronic power conversion component of claim 13 further comprising a third die including a control circuit electrically coupled to the first GaN-based die, and attached to the first die pad.

15. An electronic component comprising:

a first lead, a second lead and a third lead;

a first GaN-based semiconductor die having a bottom surface opposite a top surface, wherein the bottom surface is mounted to the first lead and the top surface includes a first power transistor having a first source terminal, a first drain terminal and a first input terminal, and wherein the first source terminal is electrically coupled to the first lead, the first drain terminal is coupled to the second lead and the first input terminal is coupled to the third lead.

16. The electronic component of claim 15 wherein a plurality of wirebonds electrically couple the first source terminal to the first lead.

17. The electronic component of claim 15 wherein the electronic package has a fourth lead that is a kelvin connection to the first source terminal.

18. An electronic power conversion component comprising:

an electrically conductive package base comprising a plurality of leads and a die pad;

a first GaN-based die secured to the die pad and including a first power transistor having a first source terminal and a first drain terminal, wherein the first source terminal is electrically coupled to the die pad;

an insulative substrate secured to the die pad and having an electrically conductive top surface;

a second GaN-based die secured to the electrically conductive top surface and including a second power transistor having a second source terminal and a second drain terminal, wherein the second source terminal is electrically coupled to the electrically conductive top surface;

a switch-node connection formed within the electronic power conversion component between the first drain terminal and the electrically conductive top surface; and

an encapsulant formed over the first and second GaN-based dies, the insulative substrate and at least a top surface of the electrically conductive package base.

19. The electronic power conversion component of claim 18 further comprising a third die secured to the die pad and including control circuitry configured to control the operation of the first and the second power transistors.

20. The electronic power conversion component of claim 18 further comprising a bootstrap capacitor disposed within the power conversion component and attached to the electrically conductive top surface of the insulative substrate.