Multilayer pillar for reduced stress interconnect and method of making same

• US 9,640,501 B2
• Filed: 10/29/2014
• Issued: 05/02/2017
• Est. Priority Date: 10/11/2007
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Jadhav, Virendra R., Semkow, Krystyna W., Srivastava, Kamalesh K., Sundlof, Brian R.
• Primary Examiner(s): Montalvo, Eva Y
• Assistant Examiner(s): Doan, Nga
• Application Number:
  US14/526,665
• Publication Number:
  US 20150054152A1
• Time in Patent Office: 916 Days
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05099 Material
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/05666 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/1145 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/11452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/11462 Electroplating
• CPC Class Codes: H01L 2224/11901 with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13005 Structure
• CPC Class Codes: H01L 2224/13013 being rectangular or square
• CPC Class Codes: H01L 2224/13023 the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/1308 being stacked
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13171 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/13599 : Material
• CPC Class Codes: H01L 2224/13655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13666 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/13671 : Chromium [Cr] as principal constituent
• CPC Class Codes: H01L 2224/13684 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16235 : the bump connector connecting to a via metallisation of the item
• CPC Class Codes: H01L 2224/29099 : Material
• CPC Class Codes: H01L 2224/29599 : Material
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 23/562 : Protection against mechanical damage H01L23/02, H01L23/28 take precedence
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01024 : Chromium [Cr]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01049 : Indium [In]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/2064 : larger or equal to 1 micron less than 100 microns
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 2924/35121 : Peeling or delaminating
• CPC Class Codes: H01L 2924/37001 : Yield
• CPC Class Codes: H01L 2924/384 : Bump effects
• CPC Class Codes: Y10T 156/10 : Methods of surface bonding and/or assembly therefor

Abstract

A multi-layer pillar and method of fabricating the same is provided. The multi-layer pillar is used as an interconnect between a chip and substrate. The pillar has at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions.

Claims

1. A structure comprising a modulated copper pillar including:

a barrier and adhesion layer that connects the modulated copper pillar to a chip;

a seed layer contacting the barrier and adhesion layer;

a first copper layer contacting the seed layer;

a second copper layer contacting a solder material; and

at least one low strength, high ductility deformation region configured to absorb force imposed during chip assembly and thermal excursions, wherein the at least one low strength, high ductility deformation region is between the first copper layer and the second copper layer and has a modulus of elasticity less than copper.

2. The structure of claim 1, wherein the barrier and adhesion layer prevents diffusion of materials between the chip and materials of the modulated copper pillar.

3. The structure of claim 1, wherein the solder material contacts a via in a substrate.

4. The structure of claim 1, further comprising:

a first nickel layer between and contacting the first copper layer and the at least one low strength, high ductility deformation region; and

a second nickel layer between and contacting the second copper layer and the at least one low strength, high ductility deformation region.

5. The structure of claim 1, wherein a vertical sidewall of the first copper layer is aligned with both a vertical sidewall of the intermediate layer and a vertical sidewall of the second copper layer.

6. The structure of claim 1, wherein the at least one low strength, high ductility deformation region comprises two separate low strength, high ductility deformation regions between the first copper layer and the second copper layer.

7. The structure of claim 6, further comprising a third copper layer between the two separate low strength, high ductility deformation regions.

8. The structure of claim 1, wherein the at least one low strength, high ductility deformation region includes one of gold, aluminum and silver.

9. The structure of claim 8, wherein the at least one low strength, high ductility deformation region is about 0.2 to 1 microns in thickness.

10. The structure of claim 1, further comprising:

a first protective layer interposed at an interface between the uppermost surface of the at least one low strength, high ductility deformation region and the first upper copper layer; and

a second protective layer interposed at an interface between the lowermost surface of the second copper layer and the at least one low strength, high ductility deformation region and the lower copper layer.

11. The structure of claim 10, wherein:

the first protective layer is a layer of nickel covering the entire uppermost surface of the at least one low strength, high ductility deformation region; and

the second protective layer is another layer of nickel covering the entire lowermost most surface of the at least one low strength, high ductility deformation region.

12. An interconnect pillar between a chip and a substrate, the interconnect pillar comprising:

a first copper layer connected to the chip by a barrier and adhesion layer;

a second copper layer connected to a via in the substrate by a solder layer;

an intermediate layer interposed between the first copper layer and the second copper layer, the intermediate layer having a lower modulus of elasticity than that of the first copper layer and the second copper layer, the intermediate layer being structured to absorb stress imposed during a cooling cycle of an interconnect process which would otherwise be imparted to a chip.

13. The interconnect pillar of claim 12, wherein the intermediate layer is one of Aluminum, Gold and Silver.

14. The interconnect pillar of claim 12, wherein the intermediate layer is configured to slide or tilt during a heating cycle of the interconnect process.

15. The interconnect pillar of claim 12, further comprising a second intermediate layer between the second copper layer and a third copper layer.

16. The interconnect pillar of claim 12, wherein the intermediate layer is configured to slide or tilt during a heating cycle of the interconnect process with the chip.

17. The interconnect pillar of claim 12, wherein the first copper layer is on and contacting a seed layer that is on and contacting the barrier and adhesion layer.

18. The interconnect pillar of claim 12, wherein a sidewall of the first copper layer is aligned with a sidewall of the intermediate layer.

19. The interconnect pillar of claim 18, wherein the sidewall of the intermediate layer is aligned with a sidewall of the second copper layer.