Multi-die package with bridge layer and method for making the same

• US 9,640,521 B2
• Filed: 01/02/2015
• Issued: 05/02/2017
• Est. Priority Date: 09/30/2014
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Wei Sen, Chen, Yu-Feng, Chen, Chen-Shien, Lii, Mirng-Ji
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US14/588,715
• Publication Number:
  US 20160093597A1
• Time in Patent Office: 851 Days
• Field of Search: 257666, 257685, 257723, 257733, 257778
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 21/4853 Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
• CPC Class Codes: H01L 21/563 Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 22/14 for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
• CPC Class Codes: H01L 22/20 Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/0237 Disposition of the redistribution layers
• CPC Class Codes: H01L 2224/02375 Top view
• CPC Class Codes: H01L 2224/0239 Material of the redistribution layers
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/03464 Electroless plating
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05111 Tin [Sn] as principal constituent
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• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
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• CPC Class Codes: H01L 2224/05164 : Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05554 : being square
• CPC Class Codes: H01L 2224/05555 : being circular or elliptic
• CPC Class Codes: H01L 2224/056 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/05611 : Tin [Sn] as principal constituent
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• CPC Class Codes: H01L 2224/11 : Manufacturing methods
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• CPC Class Codes: H01L 2224/11334 : using preformed bumps
• CPC Class Codes: H01L 2224/1141 : in liquid form
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• CPC Class Codes: H01L 2224/11462 : Electroplating
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• CPC Class Codes: H01L 2224/13022 : the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13111 : Tin [Sn] as principal constituent
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• CPC Class Codes: H01L 2224/13294 : with a principal constituent of the material being a liquid not provided for in groups H01L2224/132 - H01L2224/13291
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• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/141 : Disposition
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• CPC Class Codes: H01L 2224/16106 : the bump connector connecting one bonding area to at least two respective bonding areas
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• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/2405 : Shape
• CPC Class Codes: H01L 2224/24105 : Connecting bonding areas at different heights
• CPC Class Codes: H01L 2224/24146 : the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/24147 : the HDI interconnect not connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted, e.g. the upper semiconductor or solid-state body being mounted in a cavity or on a protrusion of the lower semiconductor or solid-state body
• CPC Class Codes: H01L 2224/24226 : the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/24227 : the HDI interconnect not connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the semiconductor or solid-state body being mounted in a cavity or on a protrusion of the item
• CPC Class Codes: H01L 2224/245 : Material
• CPC Class Codes: H01L 2224/2919 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/29191 : The principal constituent being an elastomer, e.g. silicones, isoprene, neoprene
• CPC Class Codes: H01L 2224/2929 : with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
• CPC Class Codes: H01L 2224/293 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/32106 : the layer connector connecting one bonding area to at least two respective bonding areas
• CPC Class Codes: H01L 2224/32145 : the bodies being stacked
• CPC Class Codes: H01L 2224/32225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/33505 : Layer connectors having different materials
• CPC Class Codes: H01L 2224/45099 : Material
• CPC Class Codes: H01L 2224/48091 : Arched
• CPC Class Codes: H01L 2224/48145 : the bodies being stacked
• CPC Class Codes: H01L 2224/48227 : connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48464 : the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
• CPC Class Codes: H01L 2224/73204 : the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/73207 : Bump and wire connectors
• CPC Class Codes: H01L 2224/73209 : Bump and HDI connectors
• CPC Class Codes: H01L 2224/73217 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/73253 : Bump and layer connectors
• CPC Class Codes: H01L 2224/73265 : Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 : Layer and HDI connectors
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81191 : wherein the bump connectors are disposed only on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/814 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/81411 : Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/81416 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/81424 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/81439 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/81444 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81447 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/81455 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/81815 : Reflow soldering
• CPC Class Codes: H01L 2224/82105 : by using a preform
• CPC Class Codes: H01L 2224/82815 : Reflow soldering
• CPC Class Codes: H01L 2224/83 : using a layer connector
• CPC Class Codes: H01L 2224/83101 : as prepeg comprising a layer connector, e.g. provided in an insulating plate member
• CPC Class Codes: H01L 2224/83104 : by applying pressure, e.g. by injection
• CPC Class Codes: H01L 2224/83862 : Heat curing
• CPC Class Codes: H01L 2224/83874 : Ultraviolet [UV] curing
• CPC Class Codes: H01L 2224/8592 : Applying permanent coating, e.g. protective coating
• CPC Class Codes: H01L 2224/92 : Specific sequence of method steps
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/92125 : the second connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92133 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/92144 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92147 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/92163 : the second connecting process involving a bump connector
• CPC Class Codes: H01L 2224/92242 : the first connecting process involving a layer connector
• CPC Class Codes: H01L 2224/92244 : the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2224/92247 : the second connecting process involving a wire connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/0651 : Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/3185 : the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49811 : Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads H01L23/49827 takes precedence
• CPC Class Codes: H01L 23/49838 : Geometry or layout
• CPC Class Codes: H01L 23/5381 : Crossover interconnections, e.g. bridge stepovers
• CPC Class Codes: H01L 23/5382 : Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 23/5385 : Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 24/02 : Bonding areas on insulating substrates, e.g. chip carriers, H01L23/49816, H01L23/49838, H01L23/5389; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/06 : of a plurality of bonding areas
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/24 : of an individual high density interconnect connector
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/33 : of a plurality of layer connectors
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/82 : by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 24/83 : using a layer connector
• CPC Class Codes: H01L 24/85 : using a wire connector wire bonding in general B23K20/004
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 25/0652 : the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 25/18 : the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
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• CPC Class Codes: H01L 2924/0665 : Epoxy resin
• CPC Class Codes: H01L 2924/10155 : being other than a cuboid
• CPC Class Codes: H01L 2924/10156 : at the periphery
• CPC Class Codes: H01L 2924/1431 : Logic devices
• CPC Class Codes: H01L 2924/1434 : Memory
• CPC Class Codes: H01L 2924/1436 : Dynamic random-access memory [DRAM]
• CPC Class Codes: H01L 2924/1437 : Static random-access memory [SRAM]
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3512 : Cracking

Abstract

A package structure includes a substrate having a first bond pad layer. A silicon bridge layer having one or more redistribution layers therein. The silicon bridge layer has a second bond pad, and the silicon bridge layer is attached to the substrate by an adhesive layer. A first die is coupled to the substrate and the silicon bridge layer. A second die is coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers. Power and/or ground connectors are coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die.

Claims

1. A package comprising:

a semiconductor substrate having a first bond pad;

a silicon bridge layer having one or more redistribution layers therein, the silicon bridge layer having a second bond pad, the silicon bridge layer being attached to the semiconductor substrate by an adhesive layer;

a first die coupled to the semiconductor substrate and the silicon bridge layer, the first die overlying a sidewall of the silicon bridge layer;

a second die coupled to the silicon bridge layer, wherein the first die and the second die communicate with one another by way of the one or more redistribution layers; and

power and/or ground connectors coupled to the first bond pad and the second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second die, wherein the first bond pad is positioned on the semiconductor substrate so it is outside of a lateral extent of the silicon bridge layer.

2. The package of claim 1, wherein the adhesive layer comprises a die attachment film (DAF), an epoxy, or a glue.

3. The package of claim 1, further comprising an isolation layer on sides and a portion of a top surface of the silicon bridge layer to electrically isolate the silicon bridge layer from the power and/or ground connectors, and wherein the isolation layer comprises a polyimide, molding compound, epoxy, MUF material, or combinations thereof.

4. The package of claim 1, wherein the first die comprises a logic die and the second die comprises a memory die, and further wherein the memory die comprises a Dynamic Random Access Memory (DRAM) die, Static Random Access Memory (SRAM) die, hybrid memory (HBM) cube die, or combinations thereof.

5. The package of claim 1, wherein the power and/or ground connectors comprise bond wires.

6. The package of claim 1, wherein the power and/or ground connectors comprise solder bumps or solder balls.

7. The package of claim 1, wherein the first die is electrically coupled to the semiconductor substrate and the silicon bridge layer by a plurality of copper pillars or copper posts.

8. The package of claim 1, wherein the second die is electrically coupled to the silicon bridge layer by a plurality of copper pillars or copper posts.

9. The package of claim 1, wherein a first underfill is disposed between the first die and a portion of the semiconductor substrate and between the first die and a first portion of the silicon bridge layer and a second underfill between the second die and a second portion of the silicon bridge layer, opposite the first portion of the silicon bridge layer.

10. A package structure comprising:

a semiconductor substrate having at least one first bond pad thereon;

a silicon bridge layer having one or more redistribution layers disposed therein, the silicon bridge layer attached to the semiconductor substrate, the silicon bridge layer having at least one second bond pad thereon, and further the silicon bridge layer having a layer of protective coating on a surface thereof but exposing the at least one second bond pad;

a first chip coupled to the semiconductor substrate by a plurality of conductive pillars and to the silicon bridge layer by a first plurality of conductive bumps;

a second chip coupled to the silicon bridge layer by a second plurality of conductive bumps, the second chip communicating with the first chip by way of the one or more redistribution layers;

power and/or ground connectors connected between the at least one first bond pad and the at least one second bond pad for enabling grounding and/or transferring power from the semiconductor substrate to the second chip, the power and/or ground connectors being external to the silicon bridge layer and contacting a sidewall of the silicon bridge layer; and

a first underfill disposed between the first chip and a portion of the semiconductor substrate and between the first chip and a first portion of the silicon bridge layer, and a second underfill disposed between the second chip and a second portion of the silicon bridge layer, opposite the first portion of the silicon bridge layer.

11. The package structure of claim 10, wherein the layer of protective coating comprises a polyimide, molding compound, epoxy, MUF material, or combinations thereof.

12. The package structure of claim 10, wherein the first chip comprises a logic chip and the second chip comprises a memory chip and further wherein the second chip comprises a Dynamic Random Access Memory (DRAM) die, Static Random Access Memory (SRAM) die, hybrid memory (HBM) cube die, or combinations thereof.

13. The package structure of claim 10, wherein the power and/or ground connectors comprise bond wires.

14. The package structure of claim 10, wherein the power and/or ground connectors comprise solder bumps or solder balls.

15. A package comprising:

a plurality of first connectors on a top surface of a substrate;

a bridge layer attached to the substrate, the bridge layer having one or more redistribution layers therein;

a plurality of second connectors on a top surface of the bridge layer, the plurality of second connectors connected to the one or more redistribution layers;

a first die coupled to the substrate and the bridge layer, a first section of the first die overlying the bridge layer and a second section of the first die not overlying the bridge layer;

a second die coupled to the bridge layer, the one or more redistribution layers communicatively coupling the first die and the second die; and

at least one third connector coupled to at least one of the plurality of first connectors and at least one of the plurality of second connectors, the at least one third connector for enabling transferring of power from the substrate to the second die and/or grounding, the at least one third connector being external to the bridge layer and extending along a sidewall of the bridge layer.

16. The package of claim 15, wherein the bridge layer is attached to the substrate by an adhesive layer.

17. The package of claim 15, wherein the first die is coupled to the substrate by at least one fourth connector in contact with at least one of the plurality of first connectors, and wherein the first die is coupled to the bridge layer by at least one fifth connector in contact with at least one of the plurality of second connectors.

18. The package of claim 15, wherein the second die is coupled to the bridge layer by at least one sixth connector in contact with at least one of the plurality of second connectors.

19. The package of claim 15, wherein the at least one third connector comprises a solder bump, a solder ball, a conductive bump, or a conductive paste.

20. The package of claim 15, further comprising an isolation layer on at least one surface of the bridge layer.