Semiconductor device, structure and methods

• US 9,640,531 B1
• Filed: 01/28/2015
• Issued: 05/02/2017
• Est. Priority Date: 01/28/2014
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): Chen, Yu
• Assistant Examiner(s): Rahim, Nilufa
• Application Number:
  US14/607,077
• Time in Patent Office: 825 Days
• Field of Search: None
• CPC Class Codes: H01L 21/76254 with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/823871 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2224/04042 Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2225/06537 Electromagnetic shielding
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 23/552 : Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/0694 : comprising components formed on opposite sides of a semiconductor substrate
• CPC Class Codes: H01L 27/088 : the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 : complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66545 : using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66628 : recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/785 : having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78654 : Monocrystalline silicon transistors
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A 3D semiconductor device, including: a first layer including first transistors; a second layer overlaying the first layer, the second layer including second transistors, where the second layer includes at least one thru layer via with a diameter less than 200 nm, where the second layer includes an oscillator, and where the oscillator has a frequency stability of less than 100 ppm error/° C.

Claims

1. A monolithic 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer overlaying said first layer, said second layer comprising second transistors,

wherein said second layer comprises at least one thru layer via with a diameter less than 200 nm,

wherein said second layer comprises an oscillator, and

wherein said oscillator has a frequency stability of less than 100 ppm error/°

C.

2. The 3D semiconductor device according to claim 1,

wherein at least one of said second transistors has a back-bias structure.

3. The 3D semiconductor device according to claim 1, further comprising:

a plurality of thermal paths between said second transistors and a heat removal apparatus,

wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.

4. The 3D semiconductor device according to claim 1,

wherein said first layer comprises at least one first alignment mark, and

wherein said at least one thru layer via is lithographically aligned to said first alignment mark.

5. The 3D semiconductor device according to claim 1, further comprising:

a high resistivity layer disposed between said oscillator and said first layer,

wherein said high resistivity layer has an effective resistivity higher than 1 kohm-cm.

6. The 3D semiconductor device according to claim 1,

wherein said second layer comprises a radio frequency (RF) circuit, and

wherein said radio frequency (RF) circuit has substrate losses less than 0.15 dB/mm at 2 GHz.

7. The 3D semiconductor device according to claim 1,

wherein said device comprises an EMI shield structure disposed between said oscillator and at least one of said first transistors,

wherein said EMI shield structure provides shielding between said first transistors and said oscillator.

8. A monolithic 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer overlaying said first layer, said second layer comprising second transistors,

wherein said second layer comprises at least one thru layer via with a diameter less than 200 nm,

wherein said second layer comprises a radio frequency (RF) circuit, and

wherein said radio frequency (RF) circuit has substrate losses less than 0.15 dB/mm at 2 GHz.

9. The 3D semiconductor device according to claim 8,

wherein at least one of said second transistors has a back-bias structure.

10. The 3D semiconductor device according to claim 8, further comprising:

a plurality of thermal paths between said second transistors and a heat removal apparatus,

wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.

11. The 3D semiconductor device according to claim 8,

wherein said first layer comprises at least one first alignment mark, and

wherein said at least one thru layer via is lithographically aligned to said first alignment mark.

12. The 3D semiconductor device according to claim 8, further comprising:

a high resistivity layer disposed between said radio frequency (RF) circuit and said first layer,

wherein said high resistivity layer has an effective resistivity higher than 1 kohm-cm.

13. The 3D semiconductor device according to claim 8,

wherein said second layer comprises an oscillator, and

wherein said oscillator has a frequency stability of less than 100 ppm error/°

C.

14. The 3D semiconductor device according to claim 8,

wherein said device comprises an EMI shield structure disposed between said radio frequency (RF) circuit and at least one of said first transistors,

wherein said EMI shield structure provides shielding between said first transistors and said radio frequency (RF) circuit.

15. A monolithic 3D semiconductor device, comprising:

a first layer comprising first transistors;

a second layer overlaying said first layer, said second layer comprising second transistors,

wherein said second layer comprises at least one thru layer via with a diameter less than 200 nm,

wherein said second layer comprises a radio frequency (RF) circuit, and

wherein said device comprises an EMI shield structure disposed between said radio frequency (RF) circuit and at least one of said first transistors,

wherein said EMI shield structure provides shielding between said first transistors and said radio frequency (RF) circuit.

16. The 3D semiconductor device according to claim 15,

wherein said EMI shield structure provides shielding effectiveness of greater than 60 db.

17. The 3D semiconductor device according to claim 15,

at least one of said second transistors has a back-bias structure.

18. The 3D semiconductor device according to claim 15, further comprising:

a high resistivity layer disposed between said radio frequency (RF) circuit and said first layer,

wherein said high resistivity layer has an effective resistivity higher than 1 kohm-cm.

19. The 3D semiconductor device according to claim 15,

wherein said second layer comprises an oscillator, and

wherein said oscillator has a frequency stability of less than 100 ppm error/°

C.

20. The 3D semiconductor device according to claim 15, further comprising:

a plurality of thermal paths between said second transistors and a heat removal apparatus,

wherein at least one of said plurality of thermal paths comprises a thermal contact adapted to conduct heat and not conduct electricity.