Embedded DRAM in replacement metal gate technology

• US 9,640,538 B2
• Filed: 10/29/2014
• Issued: 05/02/2017
• Est. Priority Date: 10/29/2014
• Status: Expired due to Fees

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Liu, Yanxiang, Chi, Min-hwa
• Primary Examiner(s): Armand, Marc
• Assistant Examiner(s): YI, SHANNON GYUNGMEE
• Application Number:
  US14/527,278
• Publication Number:
  US 20160126245A1
• Time in Patent Office: 916 Days
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H10B 12/0385 Making a connection between the transistor and the capacitor, e.g. buried strap
• CPC Class Codes: H10B 12/0387 Making the trench
• CPC Class Codes: H10B 12/056 the transistor being a FinFET
• CPC Class Codes: H10B 12/36 the transistor being a FinFET
• CPC Class Codes: H10B 12/373 the capacitor extending under or around the transistor

Abstract

Methods for forming an eDRAM with replacement metal gate technology and the resulting device are disclosed. Embodiments include forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an ILD; removing the first and second dummy electrodes, forming first and second cavities, respectively; forming a hardmask over the substrate, exposing the first cavity; forming a deep trench in the substrate through the first cavity; removing the hardmask; and forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.

Claims

1. A method comprising:

forming first and second dummy electrodes on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an inter-layer dielectric (ILD);

removing the first and second dummy electrodes, forming first and second cavities, respectively;

forming a spin-on glass hardmask over the substrate, the spacers and ILD and filling in the first and second cavities with the spin-on glass hardmask down to an upper surface of the substrate such that the spin-on glass hardmask is in direct contact with the upper surface of the substrate;

forming a photoresist over the second cavity and exposing the first cavity;

forming a deep trench in the substrate through the first cavity;

removing the spin-on glass hardmask; and

forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.

2. The method according to claim 1, comprising forming the capacitor and the access transistor by:

forming a high-k dielectric layer and a first metal layer, sequentially, in the first cavity and deep trench and in the second cavity; and

filling the first cavity and deep trench and the second cavity with a second metal.

3. The method according to claim 1, further comprising forming source/drain regions in the substrate at opposite sides of the second dummy electrode prior to removing the dummy electrodes.

4. The method according to claim 1, comprising removing the spin-on glass hardmask by etching.

5. The method according to claim 1, comprising forming the deep trench by reactive ion etching.

6. The method according to claim 2, comprising forming the high-k dielectric layer and the first metal layer by atomic layer deposition (ALD).

7. The method according to claim 3, further comprising connecting the second metal in the second cavity to a wordline, the source region to a bitline, and the second metal in the first cavity to the drain region.

8. The method according to claim 6, comprising forming the first metal layer of titanium nitride (TiN)/tantalum nitride (TaN).

9. A method comprising:

forming first and second dummy electrodes over a silicon fin and an adjacent shallow trench isolation (STI) region formed on a substrate, each dummy electrode having spacers at opposite sides and being surrounded by an inter-layer dielectric (ILD);

removing the first and second dummy electrodes, forming first and second cavities, respectively;

forming a spin-on glass hardmask over the substrate, the spacers and ILD and filling in the first and second cavities with the spin-on glass hardmask down to an upper surface of the substrate such that the spin-on glass hardmask is in direct contact with the upper surface of the substrate;

forming a photoresist over the second cavity and exposing a portion of the first cavity over the STI region;

forming a deep trench in the STI region through the portion of the first cavity;

removing the spin-on glass hardmask; and

forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity.

10. The method according to claim 9, comprising forming the capacitor and the access transistor by:

forming a high-k dielectric layer and a first metal layer, sequentially, in the first cavity and deep trench and in the second cavity; and

filling the first cavity and deep trench and the second cavity with a second metal.

11. The method according to claim 9, further comprising epitaxially growing source/drain regions on the silicon fin at opposite sides of the second dummy electrode prior to removing the dummy electrodes.

12. The method according to claim 9, comprising removing the spin-on glass hardmask by etching.

13. The method according to claim 9, comprising forming the deep trench by reactive ion etching.

14. The method according to claim 10, comprising forming the high-k dielectric layer and the first metal layer by atomic layer deposition (ALD).

15. The method according to claim 11, further comprising connecting the second metal in the second cavity to a wordline, the source region to a bitline, and the second metal in the first cavity to the drain region.

16. The method according to claim 14, comprising forming the first metal layer of titanium nitride (TiN)/tantalum nitride (TaN).

17. A method comprising:

forming first and second dummy electrodes over a substrate,

forming source/drain regions at opposite sides of the second dummy electrode;

forming spacers at opposite sides of each of the first and second dummy electrodes and forming an inter-layer dielectric (ILD) over the substrate;

chemical mechanical polishing (CMP) the ILD down to a top surface of the first and second dummy electrodes;

removing the first and second dummy electrodes, forming first and second cavities, respectively;

spinning on a spin-on glass hardmask over the substrate, the spacers and ILD and filling in the first and second cavities with the spin-on glass hardmask down to an upper surface of the substrate such that the spin-on glass hardmask is in direct contact with the upper surface of the substrate;

forming a photoresist over the second cavity and exposing the first cavity;

etching a deep trench through the first cavity;

removing the spin-on glass hardmask; and

forming a capacitor in the first cavity and deep trench and concurrently forming an access transistor in the second cavity by;

depositing a high-k dielectric layer and a titanium nitride (TiN)/tantalum nitride (TaN) layer, sequentially by atomic layer deposition (ALD), in the first cavity and deep trench and in the second cavity; and

filling the first cavity and deep trench and the second cavity with a metal.

18. The method of claim 17, further comprising:

forming silicon fins separated by shallow trench isolation (STI) regions on the substrate;

forming the dummy electrodes over the silicon fins and STI regions; and

forming the deep trench in an STI region.