Thin film transistor array panel and manufacturing method thereof

• US 9,640,566 B2
• Filed: 09/16/2014
• Issued: 05/02/2017
• Est. Priority Date: 11/01/2012
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Park, Ji-Young, Jeong, Yu-Gwang, Kim, Sang Gab, Lee, Joon Geol
• Primary Examiner(s): Perkins, Pamela E
• Application Number:
  US14/487,300
• Publication Number:
  US 20150072484A1
• Time in Patent Office: 959 Days
• CPC Class Codes: G02F 1/134363 for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
• CPC Class Codes: G02F 1/136227 Through-hole connection of the pixel electrode to the active element through an insulation layer
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1259 Multistep manufacturing methods
• CPC Class Codes: H01L 29/66765 Lateral single gate single channel transistors with inverted structure, i.e. the channel layer is formed after the gate
• CPC Class Codes: H01L 29/78669 with inverted-type structure, e.g. with bottom gate
• CPC Class Codes: H01L 29/78678 with inverted-type structure, e.g. with bottom gate

Abstract

A thin film transistor array panel includes a substrate, gate lines, each including a gate pad, a gate insulating layer, data lines, each including a data pad connected to a source and drain electrode, a first passivation layer disposed on the data lines and the drain electrode, a first electric field generating electrode, a second passivation layer disposed on the first electric field generating electrode, and a second electric field generating electrode. The gate insulating layer and the first and second passivation layers include a first contact hole exposing a part of the gate pad, the first and second passivation layers include a second contact hole exposing a part of the data pad, and at least one of the first and second contact holes have a positive taper structure having a wider area at an upper side than at a lower side.

Claims

1. A method of manufacturing a thin film transistor array panel, comprising:

forming a plurality of gate lines on a substrate, wherein each gate line comprises a gate pad;

forming a gate insulating layer on the plurality of gate lines;

forming a semiconductor on the gate insulating layer;

forming a plurality of data lines on the semiconductor, wherein each data line comprises a data pad connected to a source electrode and a drain electrode;

forming a first passivation layer on the plurality of data lines and the drain electrode;

forming a first electric field generating electrode on the first passivation layer;

forming a second passivation layer on the first electric field generating electrode, the second passivation layer comprising a first layer on the first passivation layer and a second layer on the first layer; and

forming a second electric field generating electrode on the second passivation layer,

wherein an etching speed of the first passivation layer is slower than an etching speed of the second passivation layer and an etching speed of the second layer of the second passivation layer is faster than an etching speed of the first layer of the second passivation layer, and

wherein the first passivation layer is formed at a temperature lower than that of the gate insulating layer, the first layer of the second passivation layer is formed at a temperature lower than that of the first passivation layer, and the second layer of the second passivation layer is formed at a temperature lower than that of the first layer of the second passivation layer.

2. The method of claim 1, wherein the etching speed of the first layer of the second passivation layer is about equal to or faster than the etching speed of the first passivation layer.

3. The method of claim 1, wherein an etching speed of the gate insulating layer is slower than the etching speed of the first passivation layer.

4. The method of claim 1, further comprising:

forming a contact hole by etching the second passivation layer, wherein the contact hole is formed to have a positive taper structure having a wider area at an upper side than at a lower side.

5. The method of claim 4, further comprising:

forming an organic insulating layer between the first passivation layer and the second passivation layer, wherein the organic insulating layer is not formed around the contact hole.

6. The method of claim 1, further comprising:

forming a first contact hole exposing a part of the gate pad in the gate insulating layer, the first passivation layer, and the second passivation layer; and

forming a second contact hole exposing a part of the data pad in the first passivation layer and the second passivation layer.

7. The method of claim 6, wherein at least one of the first contact hole and the second contact hole have a positive taper structure having a wider area at an upper side than at a lower side.

8. The method of claim 7, wherein the first passivation layer and the second passivation layer are inorganic materials.

9. A method of manufacturing a thin film transistor array panel, comprising:

forming a plurality of gate lines on a substrate, wherein each gate line comprises a gate pad;

forming a gate insulating layer on the plurality of gate lines;

forming a semiconductor on the gate insulating layer;

forming a plurality of data lines on the semiconductor, wherein each data line comprises a data pad connected to a source electrode and a drain electrode;

forming a first passivation layer on the plurality of data lines and the drain electrode;

forming a first electric field generating electrode on the first passivation layer;

forming a second passivation layer on the first electric field generating electrode;

forming a second electric field generating electrode on the second passivation layer,

wherein an etching speed of the first passivation layer is slower than an etching speed of the second passivation layer; and

forming an organic insulating layer between the first passivation layer and the second passivation layer, wherein the organic insulating layer is not formed in regions corresponding to the gate pad and the data pad.

10. The method of claim 9, further comprising:

forming a first contact hole exposing a part of the gate pad in the gate insulating layer, the first passivation layer, and the second passivation layer.

11. The method of claim 10, wherein the first contact hole is formed to have a positive taper structure having a wider area at an upper side than at a lower side.

12. The method of claim 9, further comprising:

forming a second contact hole exposing a part of the data pad in the first passivation layer and the second passivation layer.

13. The method of claim 12, wherein the second contact hole is formed to have the positive taper structure.

14. A method of manufacturing a thin film transistor array panel, comprising:

forming a plurality of gate lines on a substrate, wherein each gate line comprises a gate pad;

forming a gate insulating layer on the plurality of gate lines;

forming a semiconductor on the gate insulating layer;

forming a plurality of data lines on the semiconductor, wherein each data line comprises a data pad connected to a source electrode and a drain electrode;

forming a first passivation layer on the plurality of data lines and the drain electrode;

forming a first electric field generating electrode on the first passivation layer;

forming a second passivation layer on the first electric field generating electrode; and

forming a second electric field generating electrode on the second passivation layer,

wherein an etching speed of the first passivation layer is slower than an etching speed of the second passivation layer,

wherein a ratio of a combination concentration of nitrogen and hydrogen to a combination concentration of silicon and hydrogen of the first passivation layer is larger than a ratio of a combination concentration of nitrogen and hydrogen to a combination concentration of silicon and hydrogen of the second passivation layer.

15. The method of claim 14, wherein forming the second passivation layer comprises:

forming a first layer of the second passivation layer on the first passivation layer; and

forming a second layer of the second passivation layer on the first layer, wherein

the ratio of a combination concentration of nitrogen and hydrogen to a combination concentration of silicon and hydrogen of the first passivation layer is about equal to or smaller than a ratio of a combination concentration of nitrogen and hydrogen to a combination concentration of silicon and hydrogen of the first layer of the second passivation layer, and

the ratio of a combination concentration of nitrogen and hydrogen to a combination concentration of silicon and hydrogen of the first layer of the second passivation layer is smaller than a ratio of a combination concentration of nitrogen and hydrogen to a combination concentration of silicon and hydrogen of the second layer of the second passivation layer.