Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device

• US 9,640,636 B1
• Filed: 06/02/2016
• Issued: 05/02/2017
• Est. Priority Date: 06/02/2016
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Bentley, Steven J., Zhang, John H., Lim, Kwan-Yong, Niimi, Hiroaki
• Primary Examiner(s): Lee, Cheung
• Application Number:
  US15/171,795
• Time in Patent Office: 334 Days
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/78642 Vertical transistors

Abstract

One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.

Claims

1. A method of forming a vertical transistor device, the method comprising:

forming an initial vertically oriented channel semiconductor structure having a first height above a substrate;

forming a sacrificial spacer structure adjacent said initial vertically oriented channel semiconductor structure;

with said sacrificial spacer structure in position, performing at least one process operation to define a self-aligned bottom source/drain region for said device that is self-aligned with respect to said sacrificial spacer structure;

with said sacrificial spacer structure in position, forming an isolation region in said substrate;

with said sacrificial spacer structure in position, forming a bottom source/drain electrode above said isolation region, wherein said bottom source/drain electrode is conductively coupled to said self-aligned bottom source/drain region;

removing said sacrificial spacer structure; and

forming a bottom spacer material around said initial vertically oriented channel semiconductor structure above said bottom source/drain electrode.

2. The method of claim 1, wherein said self-aligned bottom source/drain region comprises an outer perimeter that generally corresponds to an outer perimeter of said sacrificial spacer structure at a base of said sacrificial spacer structure.

3. The method of claim 1, wherein said sacrificial spacer structure comprises at least one layer of material.

4. The method of claim 1, wherein said sacrificial spacer structure is formed on and in contact with a sidewall of said initial vertically oriented channel semiconductor structure and wherein a bottom surface of said sacrificial spacer structure is positioned on and in contact with an upper surface of said bottom source/drain electrode.

5. The method of claim 1, wherein, prior to performing said at least one process operation, the method further comprises performing at least one ion implantation process to introduce dopants into at least said substrate.

6. The method of claim 1, wherein, after performing said at least one process operation, the method further comprises performing at least one ion implantation process to introduce dopants into at least said substrate.

7. The method of claim 1, wherein performing said at least one process operation defines a final vertically oriented channel semiconductor structure having a second height that is greater than said first height.

8. The method of claim 7, wherein performing said at least one process operation comprises:

performing an etching process to form a first trench in said substrate that defines said final vertically oriented channel semiconductor structure to said second height and defines a lower portion of said final vertically oriented channel semiconductor structure that has a first lateral width in a first direction that is greater than a corresponding lateral width of said initial vertically oriented channel semiconductor structure in said first direction.

9. The method of claim 8, wherein performing said at least one process operation further comprises:

performing a recess etching process to reduce said first lateral width of said lower portion of said final vertically oriented channel semiconductor structure to a second lateral width that is less than said first lateral width;

forming an epi semiconductor material in said first trench and on an in contact with said lower portion of said final vertically oriented channel semiconductor structure having said second lateral width; and

performing an etching process to remove portions of said epi semiconductor material that are not covered by said sacrificial spacer structure, wherein said self-aligned bottom source/drain region comprises said epi semiconductor material.

10. The method of claim 1, further comprising:

forming a sacrificial material layer above said bottom spacer material, said sacrificial material layer having an upper surface;

forming a non-sacrificial spacer structure adjacent final vertically oriented channel semiconductor structure and above said upper surface of said sacrificial material layer;

after forming said non-sacrificial spacer structure, forming a top source/drain region for said device;

forming a protective cap layer above said top source/drain region;

removing said sacrificial material layer so as to define a replacement gate cavity between a bottom surface of said non-sacrificial spacer structure and said bottom spacer material; and

forming a self-aligned final replacement gate structure in said replacement gate cavity, wherein said self-aligned final replacement gate structure comprises an outer perimeter that generally corresponds to an outer perimeter of said protective cap layer at a base of said protective cap layer or to an outer perimeter of said non-sacrificial spacer structure at a base of said non-sacrificial spacer structure.

11. The method of claim 10, wherein an outer side surface of said self-aligned final replacement gate structure is substantially vertically aligned with an outer side surface of said protective cap layer or with an outer side surface of said non-sacrificial spacer structure.

12. The method of claim 10, wherein said non-sacrificial spacer structure is formed on and in contact with a sidewall of said final vertically oriented channel semiconductor structure and wherein a bottom surface of said non-sacrificial spacer structure is positioned on and in contact with an upper surface of said self-aligned final replacement gate structure.

13. The method of claim 10, wherein forming said self-aligned final replacement gate structure in said replacement gate cavity comprises depositing a plurality of gate material layers within said replacement gate cavity and performing at least one anisotropic etching process to remove portions of said plurality of gate material layers that are not covered by said protective cap layer or said non-sacrificial spacer structure.

14. The method of claim 10, wherein forming said self-aligned final replacement gate structure in said replacement gate cavity comprises:

performing a first conformal deposition process to form a layer of high-k insulating material on and in contact with sidewalls of said final vertically oriented channel semiconductor structure within said replacement gate cavity;

performing a second conformal deposition process to form a metal-containing layer within said replacement gate cavity and on and in contact with said layer of high-k insulating material;

forming a conductive fill material within said replacement gate cavity; and

performing at least one anisotropic etching process to remove portions of said layer of high-k insulating material, said metal-containing layer and said conductive fill material that are not covered by said protective cap layer or said non-sacrificial spacer structure.

15. The method of claim 10, wherein said bottom spacer material comprises silicon nitride, said sacrificial material layer comprises silicon dioxide, a sidewall spacer comprises SiOCN and said replacement gate structure comprises a high-k gate insulation layer, a work function adjusting metal-containing layer and a conductive fill layer.

16. The method of claim 1, wherein said vertical transistor device is one of an N-type device or a P-type device.

17. A method of forming a vertical transistor device, the method comprising:

forming an initial vertically oriented channel semiconductor structure having a first height above a substrate;

forming a sacrificial spacer structure adjacent said initial vertically oriented channel semiconductor structure;

with said sacrificial spacer structure in position, performing at least one process operation to define a self-aligned bottom source/drain region for said device that is self-aligned with respect to said sacrificial spacer structure and to define a final vertically oriented channel semiconductor structure having a second height that is greater than said first height, wherein said self-aligned bottom source/drain region comprises an outer perimeter that generally corresponds to an outer perimeter of said sacrificial spacer structure at a base of said sacrificial spacer structure;

with said sacrificial spacer structure in position, forming an isolation region in said substrate;

with said sacrificial spacer structure in position, forming a bottom source/drain electrode above said isolation region, wherein said bottom source/drain electrode is conductively coupled to said self-aligned bottom source/drain region;

removing said sacrificial spacer structure; and

forming a bottom spacer material around said final vertically oriented channel semiconductor structure above said bottom source/drain electrode.

18. The method of claim 17, wherein performing said at least one process operation comprises performing at least one etching process to define a trench in said substrate that defines a lower portion of said final vertically oriented channel semiconductor structure that has a first lateral width in a first direction that is greater than a corresponding lateral width of said initial vertically oriented channel semiconductor structure in said first direction.

19. The method of claim 18, wherein performing said at least one process operation further comprises:

performing a recess etching process to reduce said first lateral width of said lower portion of said final vertically oriented channel semiconductor structure to a second lateral width that is less than said first lateral width;

forming an epi semiconductor material in said trench and on an in contact with said lower portion of said final vertically oriented channel semiconductor structure having said second lateral width; and

performing an etching process to remove portions of said epi semiconductor material that are not covered by said sacrificial spacer structure, wherein said self-aligned bottom source/drain region comprises said epi semiconductor material.

20. The method of claim 17, further comprising:

forming a sacrificial material layer above said bottom spacer material, said sacrificial material layer having an upper surface;

forming a non-sacrificial spacer structure adjacent said final vertically oriented channel semiconductor structure and above said upper surface of said sacrificial material layer;

after forming said non-sacrificial spacer structure, forming a top source/drain region for said device;

forming a protective cap layer above said top source/drain region;

removing said sacrificial material layer so as to define a replacement gate cavity between a bottom surface of said non-sacrificial spacer structure and said bottom spacer material; and

forming a self-aligned final replacement gate structure in said replacement gate cavity, wherein said self-aligned final replacement gate structure comprises an outer perimeter that generally corresponds to an outer perimeter of said non-sacrificial spacer structure at a base of said protective cap layer or to an outer perimeter of said non-sacrificial spacer at a base of said non-sacrificial spacer structure.

21. The method of claim 20, wherein an outer side surface of said self-aligned final replacement gate structure is substantially vertically aligned with an outer side surface of said protective cap layer or with an outer side surface of said non-sacrificial spacer structure.

22. The method of claim 20, wherein said non-sacrificial spacer structure is formed on and in contact with a sidewall of said final vertically oriented channel semiconductor structure and wherein a bottom surface of said non-sacrificial spacer structure is positioned on and in contact with an upper surface of said self-aligned final replacement gate structure.

23. The method of claim 20, wherein forming said self-aligned final replacement gate structure in said replacement gate cavity comprises depositing a plurality of gate material layers within said replacement gate cavity and performing at least one anisotropic etching process to remove portions of said plurality of gate material layers that are not covered by said protective cap layer or said non-sacrificial spacer structure.

24. The method of claim 20, wherein forming said self-aligned final replacement gate structure in said replacement gate cavity comprises:

performing a first conformal deposition process to form a layer of high-k insulating material on and in contact with sidewalls of said final vertically oriented channel semiconductor structure within said replacement gate cavity;

performing a second conformal deposition process to form a metal-containing layer within said replacement gate cavity and on and in contact with said layer of high-k insulating material;

forming a conductive fill material within said replacement gate cavity; and

performing at least one anisotropic etching process to remove portions of said layer of high-k insulating material, said metal-containing layer and said conductive fill material that are not covered by said protective cap layer or said non-sacrificial spacer structure.