Methods of forming replacement gate structures and bottom and top source/drain regions on a vertical transistor device
First Claim
1. A method of forming a vertical transistor device, the method comprising:
- forming an initial vertically oriented channel semiconductor structure having a first height above a substrate;
forming a sacrificial spacer structure adjacent said initial vertically oriented channel semiconductor structure;
with said sacrificial spacer structure in position, performing at least one process operation to define a self-aligned bottom source/drain region for said device that is self-aligned with respect to said sacrificial spacer structure;
with said sacrificial spacer structure in position, forming an isolation region in said substrate;
with said sacrificial spacer structure in position, forming a bottom source/drain electrode above said isolation region, wherein said bottom source/drain electrode is conductively coupled to said self-aligned bottom source/drain region;
removing said sacrificial spacer structure; and
forming a bottom spacer material around said initial vertically oriented channel semiconductor structure above said bottom source/drain electrode.
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Accused Products
Abstract
One illustrative method disclosed herein includes, among other things, forming an initial vertically oriented channel semiconductor structure having a first height above a substrate, forming a sacrificial spacer structure adjacent the initial vertically oriented channel semiconductor structure and, with the sacrificial spacer in position, performing at least one process operation to define a self-aligned bottom source/drain region for the device that is self-aligned with respect to the sacrificial spacer structure, forming an isolation region in the trench and forming a bottom source/drain electrode above the isolation region. The method also includes removing the sacrificial spacer structure and forming a bottom spacer material around the vertically oriented channel semiconductor structure above the bottom source/drain electrode.
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Citations
24 Claims
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1. A method of forming a vertical transistor device, the method comprising:
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forming an initial vertically oriented channel semiconductor structure having a first height above a substrate; forming a sacrificial spacer structure adjacent said initial vertically oriented channel semiconductor structure; with said sacrificial spacer structure in position, performing at least one process operation to define a self-aligned bottom source/drain region for said device that is self-aligned with respect to said sacrificial spacer structure; with said sacrificial spacer structure in position, forming an isolation region in said substrate; with said sacrificial spacer structure in position, forming a bottom source/drain electrode above said isolation region, wherein said bottom source/drain electrode is conductively coupled to said self-aligned bottom source/drain region; removing said sacrificial spacer structure; and forming a bottom spacer material around said initial vertically oriented channel semiconductor structure above said bottom source/drain electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
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17. A method of forming a vertical transistor device, the method comprising:
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forming an initial vertically oriented channel semiconductor structure having a first height above a substrate; forming a sacrificial spacer structure adjacent said initial vertically oriented channel semiconductor structure; with said sacrificial spacer structure in position, performing at least one process operation to define a self-aligned bottom source/drain region for said device that is self-aligned with respect to said sacrificial spacer structure and to define a final vertically oriented channel semiconductor structure having a second height that is greater than said first height, wherein said self-aligned bottom source/drain region comprises an outer perimeter that generally corresponds to an outer perimeter of said sacrificial spacer structure at a base of said sacrificial spacer structure; with said sacrificial spacer structure in position, forming an isolation region in said substrate; with said sacrificial spacer structure in position, forming a bottom source/drain electrode above said isolation region, wherein said bottom source/drain electrode is conductively coupled to said self-aligned bottom source/drain region; removing said sacrificial spacer structure; and forming a bottom spacer material around said final vertically oriented channel semiconductor structure above said bottom source/drain electrode. - View Dependent Claims (18, 19, 20, 21, 22, 23, 24)
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Specification