Secure switch assembly

• US 9,641,176 B2
• Filed: 07/21/2015
• Issued: 05/02/2017
• Est. Priority Date: 07/21/2015
• Status: Active Grant

• Current Assignee: Raytheon Company (Rtx Corporation)
• Original Assignee: Raytheon Company (Rtx Corporation)
• Inventors: Hammond, Matthew L., Cramer, Norman W., Kressig, II, Robert G.
• Primary Examiner(s): Hammond, Crystal L
• Application Number:
  US14/804,851
• Publication Number:
  US 20170026040A1
• Time in Patent Office: 651 Days
• Field of Search: None
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: H03K 19/003 Modifications for increasing the reliability for protection
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches
• CPC Class Codes: H04L 63/105 Multiple levels of security

Abstract

A secure switch assembly is provided and includes inputs respectively associated with at least first and second security levels, switch element outputs respectively associated with the at least first and second security levels and a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs. The FPGA has a first side facing the inputs and a second side facing the switch element outputs and includes a gate array. The gate array is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which each of the first security level associated inputs and switch element outputs are connectable and each of the second security level associated inputs and switch element outputs are connectable.

Claims

1. A secure switch assembly, comprising:

inputs respectively associated with at least first and second security levels;

switch element outputs respectively associated with the at least first and second security levels; and

a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs,

the FPGA having a first side facing the inputs and a second side facing the switch element outputs and comprising a gate array that is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which;

each of the first security level associated inputs and switch element outputs are connectable, and

each of the second security level associated inputs and switch element outputs are connectable.

2. The secure switch assembly according to claim 1, further comprising a backplane by which the first side of the FPGA is connectable with the inputs.

3. The secure switch assembly according to claim 1, wherein the inputs comprise single board computing elements.

4. The secure switch assembly according to claim 1, further comprising high speed switch interfaces to which the switch element outputs are connectable.

5. The secure switch assembly according to claim 1, further comprising a card on which the FPGA, the switch element outputs and the high speed switch interfaces are disposable.

6. The secure switch assembly according to claim 5, further comprising a control element disposed on the card and configured to control a programming of the FPGA.

7. The secure switch assembly according to claim 1, wherein the physical interconnections are displaced from one another in a single plane.

8. The secure switch assembly according to claim 1, wherein the physical interconnections are partially disposed in a base plane and at least one of the physical interconnections comprises:

first and second horizontal terminals in the base plane;

first and second vertical terminals coupled to the first and second horizontal terminals, respectively, which extend away from the base plane; and

a horizontal component extending between distal end of the first and second vertical terminals at a displaced plane.

9. A secure switch assembly, comprising:

computing devices each having inputs respectively associated with at least first and second security levels;

switch elements each having switch element outputs respectively associated with the at least first or second security levels; and

a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs,

the FPGA having a first side facing the inputs and a second side facing the switch element outputs and comprising a gate array that is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which;

each of the first security level associated inputs and switch element outputs are connectable for enabling computing device-switch element communication, and

each of the second security level associated inputs and switch element outputs are connectable for enabling computing device-switch element communication.

10. The secure switch assembly according to claim 9, further comprising a backplane by which the first side of the FPGA is connectable with the inputs.

11. The secure switch assembly according to claim 9, wherein the switch elements comprise high speed switch interfaces.

12. The secure switch assembly according to claim 9, further comprising a card on which the FPGA, the switch element outputs and the switch elements are disposable.

13. The secure switch assembly according to claim 12, further comprising a control element disposed on the card and configured to control a programming of the FPGA.

14. The secure switch assembly according to claim 9, wherein the physical interconnections are partially disposed in a base plane and at least one of the physical interconnections comprises:

first and second horizontal terminals in the base plane;

first and second vertical terminals coupled to the first and second horizontal terminals, respectively, which extend away from the base plane; and

a horizontal component extending between distal end of the first and second vertical terminals at a displaced plane.

15. A secure switch assembly, comprising:

first and second computing devices each having inputs associated with at least first and second security levels, respectively;

first and second switch elements each having switch element outputs associated with the at least first and second security levels, respectively; and

a field programmable gate array (FPGA) operably interposed between the inputs and the switch element outputs,

the FPGA having a first side facing the inputs and a second side facing the switch element outputs and comprising a gate array that is programmable to generate entirely separate physical interconnections extending from the first side to the second side by which;

each of the first security level associated inputs and switch element outputs are connectable for enabling first computing device-first switch element communication, and

each of the second security level associated inputs and switch element outputs are connectable for enabling second computing device-second switch element communication.

16. The secure switch assembly according to claim 15, further comprising a backplane by which the first side of the FPGA is connectable with the inputs.

17. The secure switch assembly according to claim 15, wherein the switch elements comprise high speed switch interfaces.

18. The secure switch assembly according to claim 15, further comprising a card on which the FPGA, the switch element outputs and the switch elements are disposable.

19. The secure switch assembly according to claim 18, further comprising a control element disposed on the card and configured to control a programming of the FPGA.

20. The secure switch assembly according to claim 15, wherein the physical interconnections are displaced from one another in a single plane.