Dual-loop programmable and dividerless clock generator for ultra low power applications

• US 9,641,183 B2
• Filed: 10/22/2014
• Issued: 05/02/2017
• Est. Priority Date: 10/22/2013
• Status: Active Grant

• Current Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Original Assignee: Board of Regents of the University of Michigan (University of Michigan)
• Inventors: Wentzloff, David D., Faisal, Muhammad
• Primary Examiner(s): Cole, Brandon S
• Application Number:
  US15/031,115
• Publication Number:
  US 20160269035A1
• Time in Patent Office: 923 Days
• Field of Search: 327 2- 12, 327105-123, 327141-163, 331 1 A, 331 15- 17, 375373-376
• CPC Class Codes: H03B 5/32 being a piezoelectric resonator selection of piezoelectric material H10N30/00
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03L 2207/50 All digital phase-locked loop
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0991 the oscillator being a digital oscillator, e.g. composed of a fixed oscillator followed by a variable frequency divider H03L7/0995 takes precedence; fixed oscillators with means for selecting among various phases H03L7/0814
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03L 7/113 using frequency discriminator
• CPC Class Codes: H03L 7/235 Nested phase locked loops

Abstract

A programmable clock generator is provided which is particularly suitable for low power applications. The programmable clock generator is comprised of: an oscillator circuit that generates an output signal whose frequency is set by a control signal, two feedback loops for controlling output frequency and a loop select that selects which feedback loop is operational at a given time. In operation, the frequency loop operates to coarsely adjust the frequency of the output signal; whereas, the phase loop operates to finely adjust the frequency of the output signal. The clock generator is preferably implemented by transistors operating in or near the subthreshold region.

Claims

1. A programmable clock generator, comprising:

an oscillator circuit configured to receive a control signal and generate an output signal oscillating at a frequency, where the frequency of the output signal is set in accordance with the control signal;

a frequency-locked loop circuit configured to receive a desired output frequency and the output signal from oscillator circuit, wherein the frequency-locked loop circuit oversamples the output signal from the oscillator circuit and determines the frequency of the output signal from the oversampled signal and generates an error signal without the use of a frequency divider, where the error signal indicates a difference between the desired output frequency and the determined output frequency;

a phase-locked loop circuit configured to receive a reference signal and the output signal from oscillator circuit, wherein the phase-locked loop circuit determines a phase error between the reference signal and the output signal without the use of a frequency divider and generates an error signal from the phase error, where the error signal indicates a difference between the desired output frequency and the determined output frequency;

a loop selector circuit configured to receive the error signal from the frequency-locked loop circuit and the error signal from the phase-locked loop circuit, wherein the loop selector circuit selects one of the error signals and outputs the selected error signal; and

a controller configured to receive the selected error signal from the loop selector circuit and converts the error signal to the control signal for the oscillator circuit.

2. The programmable clock generator of claim 1 wherein the oscillator circuit is implemented by a ring oscillator.

3. The programmable clock generator of claim 1 wherein the oscillator circuit is implemented with CMOS transistors, each transistor having a channel length ten times the minimum length for CMOS technology.

4. The programmable clock generator of claim 3 wherein the frequency-locked loop circuit includes an edge combiner circuit.

5. The programmable clock generator of claim 1 wherein the phase-locked loop circuit generates the error signal by taking a derivative of the phase error.

6. The programmable clock generator of claim 5 wherein the loop selector circuit enables the frequency-locked loop circuit and disables the phase-locked loop circuit when the difference indicated by the error signal received from the phase-locked loop circuit is greater than the threshold.

7. The programmable clock generator of claim 1 wherein the phase-locked loop circuit includes a time-to-digital converter circuit.

8. The programmable clock generator of claim 1 wherein the loop selector circuit enables the phase-locked loop circuit and disables the frequency-locked loop circuit when the difference indicated by the error signal received from the frequency-locked loop circuit is less than a threshold.

9. The programmable clock generator of claim 1 is implemented by transistors operating in or near subthreshold region.

10. A programmable clock generator, comprising:

an oscillator circuit configured to receive a control signal and generate an output signal oscillating at a frequency, where the frequency of the output signal is set in accordance with the control signal;

a frequency-locked loop circuit configured to receive a desired output frequency and the output signal from oscillator circuit, wherein the frequency-locked loop circuit determines frequency of the output signal and generates an error signal, where the error signal indicates a difference between the desired output frequency and the determined output frequency;

a phase-locked loop circuit configured to receive a reference signal and the output signal from oscillator circuit, wherein the phase-locked loop circuit determines a phase error between the reference signal and the output signal and generates an error signal from the phase error, where the error signal indicates a difference between the desired output frequency and the determined output frequency;

a loop selector circuit configured to receive the error signal from the frequency-locked loop circuit and the error signal from the phase-locked loop circuit, select one of the error signals and output the selected error signal, wherein the loop selector circuit enables the phase-locked loop circuit when the difference indicated by the error signal received from the frequency-locked loop circuit is less than a threshold and enables the frequency-locked loop circuit when the difference indicated by the error signal received from the phase-locked loop circuit is greater than the threshold; and

a controller configured to receive the selected error signal from the loop selector circuit and converts the error signal to the control signal for the oscillator circuit.

11. The programmable clock generator of claim 10 wherein the oscillator circuit is implemented by a ring oscillator.

12. The programmable clock generator of claim 10 wherein the oscillator circuit is implemented with CMOS transistors, each transistor having a channel length ten times the minimum length for CMOS technology.

13. The programmable clock generator of claim 10 wherein the frequency-locked loop circuit oversamples the output signal from the oscillator circuit and determines the frequency of the output signal from the oversampled signal.

14. The programmable clock generator of claim 10 wherein the phase-locked loop circuit generates the error signal by taking a derivative of the phase error.

15. The programmable clock generator of claim 10 wherein the phase-locked loop circuit includes a time-to-digital converter circuit.

16. The programmable clock generator of claim 10 wherein the loop selector circuit disables the frequency-locked loop circuit when the difference indicated by the error signal received from the frequency-locked loop circuit is less than a threshold and disables the phase-locked loop circuit when the difference indicated by the error signal received from the phase-locked loop circuit is greater than the threshold.

17. The programmable clock generator of claim 10 is implemented by transistors operating in or near subthreshold region.