Circuit arrangement and method for processing a digital video stream and for detecting a fault in a digital video stream, digital video system and computer readable program product

• US 9,641,809 B2
• Filed: 03/25/2014
• Issued: 05/02/2017
• Est. Priority Date: 03/25/2014
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Inventors: Staudenmaier, Michael Andreas, Wendel, Dirk, Osornio Lopez, Victor-Hugo
• Primary Examiner(s): Elahi, Shan
• Application Number:
  US14/224,167
• Publication Number:
  US 20150281742A1
• Time in Patent Office: 1,134 Days
• Field of Search: 37524027
• CPC Class Codes: H04N 19/89 involving methods or arrangements for detection of transmission errors at the decoder
• CPC Class Codes: H04N 7/183 for receiving images from a single remote source

Abstract

The present invention relates to a circuit arrangement for processing a digital video stream, the circuit arrangement comprising: an input interface for receiving a digital video stream, a processing circuit which is arranged to process the digital video stream, a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising: a checksum generating circuit which is arranged to generate checksums for the frames of the processed digital video stream, a memory for storing generated checksums and an analyzing device arranged to compare a currently generated checksum to a plurality of corresponding checksums of preceding frames stored in the memory and to generate an error signal if at least one predefined amount of compared checksums are matching. The present invention also relates to a digital video system, a method for processing a digital video stream and a computer readable program product.

Claims

1. A circuit arrangement for processing a digital video stream and for detecting a fault in the processed digital video stream, the circuit arrangement comprising:

an input interface for receiving an digital video stream, the digital video stream comprises information of a sequence of frames, the sequence of frames including first, second, and third frames;

a processing circuit which is arranged to process the digital video stream and to provide the processed digital video stream to an output interface; and

a hang-up detecting circuit for detecting a fault in the processed digital video stream, the hang-up detecting circuit comprising;

a checksum generating circuit which is arranged to generate a checksum for at least a part of each frame of the sequence including a first checksum for the first frame, a second checksum for the second frame, and a third checksum for the third frame,

a memory to store a predefined amount of generated checksums including the first, second, and third checksums; and

an analyzing unit arranged to compare a currently generated checksum of a current frame of the sequence of frames of the processed digital video stream with a plurality of corresponding checksums of preceding frames stored in the memory including the first, second, and third checksums, and to generate an error signal if at least one predefined amount of compared checksums are matching.

2. The circuit arrangement of claim 1, wherein the hang-up detecting circuit comprises a tap input which is connected to the input interface and wherein the tap input is further arranged to tap the digital video stream at the input interface in order to detect a fault in the unprocessed digital video stream.

3. The circuit arrangement of claim 1, wherein the checksum generating circuit is arranged to generate a CRC checksum.

4. The circuit arrangement of claim 1, wherein the checksum generating circuit is arranged to generate a plurality of checksums per frame of the digital video stream, in particular at least four checksums.

5. The circuit arrangement of claim 1, wherein the analysing unit comprises a hang-up counter and a decider, wherein the hang-up counter is arranged to identify the amount of checksums which are matching and wherein the decider is arranged to generate the error signal only if a predefined amount of matched checksums are identified.

6. The circuit arrangement of claim 1, wherein the analysing unit comprises a hang-up counter and a decider, wherein the hang-up counter is arranged to identify a failure in the digital video stream based on the ratio between the number of non-identical checksums and the number of identical checksums and wherein the decider is arranged to generate the error signal only if the ratio exceeds a predefined ratio.

7. The circuit arrangement of claim 1, wherein the analysing unit is coupled with the input interface and is arranged such to perform a modification of the unprocessed digital video signal if at least two compared checksums are matching and/or if an error is detected.

8. The circuit arrangement of claim 1, further comprising an interrupting device which is coupled to the analysing unit in order to receive the error signal and which is arranged to interrupt the functionality of an external video signal generating circuit, the input interface, the processing device and/or the output interface if an error signal is provided to the interrupting device.

9. The circuit arrangement of claim 1, wherein the memory is arranged to store at least one checksum per stored image frame of the generated digital video stream.

10. The circuit arrangement of claim 1, wherein the circuit arrangement is included within a digital video system, in particular an automotive video system, further comprising:

a video signal generating circuit which is coupled to the circuit arrangement and which is arranged to provide a digital video stream to the input interface of the circuit arrangement, and

a display device which is coupled to an output interface of the circuit arrangement and which is arranged to display the digital video stream processed by the circuit arrangement.

11. The video system of claim 10, further comprising an optical and/or acoustical error displaying device which is coupled to an error output terminal of the circuit arrangement and which based on the error signal is arranged to optically and/or acoustically indicate an error condition.

12. The video system of claim 10, wherein the video signal generating circuit is a camera.

13. The video system of claim 10, wherein the video signal generating circuit is a calculation circuit which is arranged to calculate the digital video stream based on a predefined program and/or video data.

14. A method for processing a digital video stream and for detecting a fault in the processed digital video stream, the method comprising:

processing a digital video stream wherein the digital video stream comprising information of an image;

detecting a fault for each frame of a sequence of frames of the processed digital video stream, the sequence of frames including first, second, and third frames, detecting comprising;

generating a checksum for at least a part of each frame of the sequence of frames the processed digital video stream, including a first checksum for the first frame, a second checksum for the second frame, and a third checksum for the second frame,

storing a predefined amount of generated checksums including the first, second, and third checksums in a memory,

comparing a currently generated checksum of a current frame of the sequence of frames of the processed digital video stream with a plurality of corresponding checksums of preceding frames of the same processed digital video stream stored in the memory including the first, second, and third checksums,

generating an error signal if at least a predefined amount of compared checksums are matching.

15. The method of claim 14, further comprising:

slightly modifying the unprocessed digital video stream if at least one pair of compared checksums is matching.

16. The method of claim 14, further comprising interrupting the functionality of a video signal generating circuit, an input interface, a processing device and/or an output interface if an error signal is generated.

17. The method of claim 14, wherein the subsequently generating comprises the generation of a plurality of checksums per frame of the processed digital video stream.

18. The method of claim 14, wherein the error signal is generated only if a predefined amount of matched checksums are straight successively identified.

19. A non-transitory computer readable medium comprising a memory device stores instructions which, when executed by a processor cause the processor to:

process a digital video stream wherein the digital video stream comprising information of an image;

detect a fault for each frame of a sequence of frames of the processed digital video stream, the sequence of frames including first, second, and third frames, detecting comprising;

generate a checksum for at least a part of each frame of the sequence of frames the processed digital video stream, including a first checksum for the first frame, a second checksum for the second frame, and a third checksum for the second frame,

store a predefined amount of generated checksums including the first, second, and third checksums in a memory,

compare a currently generated checksum of a current frame of the sequence of frames of the processed digital video stream with a plurality of corresponding checksums of preceding frames of the same processed digital video stream stored in the memory including the first, second, and third checksums,

generate an error signal if at least a predefined amount of compared checksums are matching.

20. The non-transitory computer readable medium of claim 19, wherein the subsequently generate the error signal comprises the generation of a plurality of checksums per frame of the processed digital video stream.