Waypoint generation for adaptive flash tuning
First Claim
1. An offline characterization system that generates, during an offline characterization phase prior to the operational lifetime of a flash memory chip, a plurality of alternative sets of read operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more n-bit control registers, and each control register stores the value of an operating parameter associated with that LUN, the offline characterization system comprising:
- (a) a set of write and erase operating parameter values stored in the control registers of the flash memory chip;
(b) a pattern generator that generates test pattern data to be written to and read from the one or more blocks of flash memory;
(c) a flash test controller that writes the test pattern data into the one or more blocks of flash memory in accordance with the set of write and erase operating parameter values, and reads the test pattern data following a simulated retention period, wherein the retention period is simulated by baking the flash memory chip using standard accelerated temperature-testing techniques; and
(d) a Vt window generator that, upon completion of the simulated retention period;
(i) performs a read sweep by invoking the flash test controller to perform a plurality of read operations, wherein each read operation includes an attempt to read the test pattern data from the one or more blocks of flash memory in accordance with a different set of read operating parameter values,(ii) identifies a Vt window in which the read operations of the read sweep successfully read the test pattern data, wherein the Vt window represents a range of threshold voltage levels, and wherein each threshold voltage level corresponds to a different set of read operating parameter values, and(iii) identifies, as an alternative set of read operating parameter values, each set of read operating parameter values corresponding to a threshold voltage level within the Vt window.
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Accused Products
Abstract
The present invention includes embodiments of systems and methods for increasing the operational efficiency and extending the estimated operational lifetime of a flash memory storage device (and its component flash memory chips, LUNs and blocks of flash memory) by monitoring the health of the device and its components and, in response, adaptively tuning the operating parameters of flash memory chips during their operational lifetime, as well as employing other less extreme preventive measures in the interim, via an interface that avoids the need for direct access to the test modes of the flash memory chips. In an offline characterization phase, “test chips” from a batch of recently manufactured flash memory chips are used to simulate various usage scenarios and measure the performance effects of writing and attempting to recover (read) test patterns written with different sets of operating parameters over time (simulating desired retention periods).
10 Citations
10 Claims
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1. An offline characterization system that generates, during an offline characterization phase prior to the operational lifetime of a flash memory chip, a plurality of alternative sets of read operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more n-bit control registers, and each control register stores the value of an operating parameter associated with that LUN, the offline characterization system comprising:
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(a) a set of write and erase operating parameter values stored in the control registers of the flash memory chip; (b) a pattern generator that generates test pattern data to be written to and read from the one or more blocks of flash memory; (c) a flash test controller that writes the test pattern data into the one or more blocks of flash memory in accordance with the set of write and erase operating parameter values, and reads the test pattern data following a simulated retention period, wherein the retention period is simulated by baking the flash memory chip using standard accelerated temperature-testing techniques; and (d) a Vt window generator that, upon completion of the simulated retention period; (i) performs a read sweep by invoking the flash test controller to perform a plurality of read operations, wherein each read operation includes an attempt to read the test pattern data from the one or more blocks of flash memory in accordance with a different set of read operating parameter values, (ii) identifies a Vt window in which the read operations of the read sweep successfully read the test pattern data, wherein the Vt window represents a range of threshold voltage levels, and wherein each threshold voltage level corresponds to a different set of read operating parameter values, and (iii) identifies, as an alternative set of read operating parameter values, each set of read operating parameter values corresponding to a threshold voltage level within the Vt window. - View Dependent Claims (2, 3, 4, 5)
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6. A method for generating, during an offline characterization phase prior to the operational lifetime of a flash memory chip, a plurality of alternative sets of read operating parameter values associated with a LUN in the flash memory chip, wherein the flash memory chip includes one or more LUNs, each LUN includes one or more blocks of flash memory and an associated set of one or more control registers, and each control register stores the value of an operating parameter associated with that LUN, the method comprising the following steps:
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(a) storing a set of write and erase operating parameter values in the control registers of the flash memory chip; (b) writing test pattern data into the one or more blocks of flash memory in accordance with the set of write and erase operating parameter values; (c) simulating a period of retention by baking the flash memory chip using standard accelerated temperature-testing techniques; (d) performing a read sweep, upon completion of the simulated retention period, by performing a plurality of read operations, wherein each read operation includes an attempt to read the test pattern data from the one or more blocks of flash memory in accordance with a different set of read operating parameter values; (e) identifying a Vt window in which the read operations of the read sweep successfully read the test pattern data, wherein the Vt window represents a range of threshold voltage levels, and wherein each threshold voltage level corresponds to a different set of read operating parameter values; and (f) identifying, as an alternative set of read operating parameter values, each set of read operating parameter values corresponding to a threshold voltage level within the Vt window. - View Dependent Claims (7, 8, 9, 10)
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Specification